Change in ...coreboot[master]: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33433
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr [15:8]> <Reg Addr[7:0]> < Data[7:0]> [Data[15:8], Data[23:16], Data{31:24]
BUG=N/A TEST=Config eDP and verify that LCD panels are working on Facebook FBG-1701 rev 0-2
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/facebook/fbg1701/mainboard.c M src/mainboard/facebook/fbg1701/mainboard.h M src/mainboard/facebook/fbg1701/ramstage.c 3 files changed, 328 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33433/1
diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c index ff2564d..40054d8 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.c +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -16,10 +16,34 @@ * GNU General Public License for more details. */
+#include <arch/io.h> #include <device/device.h> +#include <soc/smbus.h> #include "onboard.h" #include "mainboard.h"
+void mainboard_configure_edp_bridge(void) +{ + edp_data_t *edptable; + + if (((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> + CPLD_PCB_VERSION_BIT) < 7) + edptable = (edp_data_t *)mainboard_TC348860_InitTable; + else + edptable = (edp_data_t *)mainboard_B101UAN08_InitTable; + + /* reset bridge */ + outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT); + outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT); + + /* set eDP bridge to eDP 1920 */ + while (edptable->address) { + smbus_i2c_block_write(edptable->address, edptable->offset, + edptable->number_of_databytes, &edptable->data[0]); + edptable++; + }; +} + /* * Declare the resources we are using */ diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/mainboard.h index e161da0..870b02e 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.h +++ b/src/mainboard/facebook/fbg1701/mainboard.h @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Facebook, Inc + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,305 @@ #ifndef MAINBOARD_H #define MAINBOARD_H
+typedef struct { + u8 number_of_databytes; + u8 address; + u8 offset; /* register address [15:8] */ + u8 data[5]; /* First byte is register address [7:0] */ +} edp_data_t; + +static const edp_data_t mainboard_TC348860_InitTable[] = { + /* set eDP bridge to eDP 1920 */ + /* IO */ + { 5, 0x68, 0x08, {0x00, 0x01, 0x00, 0x00, 0x00 } }, + /* Boot */ + { 5, 0x68, 0x10, {0x00, 0x78, 0x69, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x04, 0x02, 0x08, 0x02, 0x00 } }, + { 5, 0x68, 0x10, {0x08, 0x23, 0x00, 0x87, 0x02 } }, + { 5, 0x68, 0x10, {0x0C, 0x19, 0x04, 0x00, 0x23 } }, + { 5, 0x68, 0x10, {0x10, 0x06, 0x00, 0x67, 0x00 } }, + { 5, 0x68, 0x10, {0x14, 0x01, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Internal */ + { 2, 0x68, 0xB0, {0x05, 0x0A, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x06, 0x03, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x07, 0x16, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x08, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x09, 0x21, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x0A, 0x07, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x14, 0x03, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* eDP */ + { 2, 0x68, 0x80, {0x03, 0x41, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB4, {0x00, 0x0D, 0x00, 0x00, 0x00 } }, + /* DPRX */ + { 2, 0x68, 0xB8, {0x8E, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8F, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x9A, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x9B, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x00, 0x0E, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x26, 0x02, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x01, 0x20, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC0, 0xF1, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC1, 0xF1, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC2, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC3, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC4, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC5, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC6, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC7, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x0B, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x33, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x5B, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x10, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x38, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x60, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x15, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x3D, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x65, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x1A, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x42, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x6A, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x1F, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x47, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x6F, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x24, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x4C, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x74, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x29, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x51, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x79, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x2E, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x56, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x7E, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x90, 0x10, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x91, 0x0F, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x92, 0xF6, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x93, 0x10, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x94, 0x0F, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x95, 0xF6, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x96, 0x10, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x97, 0x0F, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x98, 0xF6, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x99, 0x10, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x9A, 0x0F, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x9B, 0xF6, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8A, 0x03, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x96, 0x03, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0xD1, 0x07, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0xB0, 0x07, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8B, 0x04, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8C, 0x45, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8D, 0x05, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x97, 0x04, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x98, 0xE0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x99, 0x2E, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x80, {0x0E, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x14, 0x07, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Video size */ + { 5, 0x68, 0x01, {0x48, 0xB0, 0x04, 0x00, 0x00 } }, + { 5, 0x68, 0x29, {0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + /* eDP */ + { 2, 0x68, 0xB6, {0x31, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x80, {0x01, 0x14, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x80, {0x02, 0x02, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB6, {0x08, 0x0B, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x00, 0x1E, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x87, {0x00, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x50, {0x10, 0x00, 0x00, 0x9D, 0x00 } }, + { 5, 0x68, 0x00, {0x8C, 0x40, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x80, 0x02, 0x00, 0x00, 0x00 } }, + /* Link Training */ + { 2, 0x68, 0x82, {0x02, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x82, {0x03, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x82, {0x04, 0xFF, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x21, {0x58, 0x09, 0x00, 0x28, 0x00 } }, + { 5, 0x68, 0x21, {0x60, 0x07, 0x00, 0x0F, 0x00 } }, + { 5, 0x68, 0x21, {0x64, 0x28, 0x23, 0x00, 0x00 } }, + { 5, 0x68, 0x21, {0x68, 0x0E, 0x00, 0x00, 0x00 } }, + /* DSI */ + { 5, 0x68, 0x20, {0x7C, 0x81, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x20, {0x50, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x20, {0x1C, 0x01, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x20, {0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* GPIO */ + { 5, 0x68, 0x08, {0x04, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x80, 0x0F, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x84, 0x0F, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x84, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x84, 0x0F, 0x00, 0x00, 0x00 } }, + /* DSI clock */ + { 5, 0x68, 0x20, {0x50, 0x20, 0x00, 0x00, 0x00 } }, + /* LCD init */ + { 5, 0x68, 0x22, {0xFC, 0x15, 0x01, 0x00, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x8C, 0x80, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0xC7, 0x50, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0xC5, 0x50, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x85, 0x04, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x86, 0x08, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x83, 0xAA, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x84, 0x11, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x9C, 0x10, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0xA9, 0x4B, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x05, 0x11, 0x00, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x05, 0x29, 0x00, 0x81 } }, + { 5, 0x68, 0x2A, {0x10, 0x10, 0x00, 0x04, 0x80 } }, + { 5, 0x68, 0x2A, {0x04, 0x01, 0x00, 0x00, 0x00 } }, + /* Check Video */ + { 5, 0x68, 0x01, {0x54, 0x01, 0x00, 0x00, 0x00 } }, + { 5, 0x00, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00 } }, +}; + +static const edp_data_t mainboard_B101UAN08_InitTable[] = { + /* set eDP bridge to eDP 1920 */ + /* IO Voltage Setting */ + { 5, 0x68, 0x08, {0x00, 0x01, 0x00, 0x00, 0x00 } }, + /* Boot Settings */ + { 5, 0x68, 0x10, {0x00, 0x78, 0x69, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x04, 0x02, 0x08, 0x02, 0x00 } }, + { 5, 0x68, 0x10, {0x08, 0x22, 0x00, 0xA0, 0x02 } }, + { 5, 0x68, 0x10, {0x0C, 0x50, 0x04, 0x00, 0x03 } }, + { 5, 0x68, 0x10, {0x10, 0x10, 0x0D, 0x06, 0x01 } }, + { 5, 0x68, 0x10, {0x14, 0x01, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Internal PCLK settings for Non Present or REFCLK=26MHz */ + { 2, 0x68, 0xB0, {0x05, 0x0A, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x06, 0x03, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x07, 0x16, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x08, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x09, 0x21, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB0, {0x0A, 0x07, 0x00, 0x00, 0x00 } }, + /* DSI Clock setting for Non Preset or REFCLK=26MHz */ + { 5, 0x68, 0x41, {0xB0, 0xC1, 0x22, 0x04, 0x00 } }, + { 5, 0x68, 0x41, {0xBC, 0x01, 0x0E, 0x00, 0x00 } }, + { 5, 0x68, 0x41, {0xC0, 0x30, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x14, 0x03, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Additional Settng for eDP */ + { 2, 0x68, 0x80, {0x03, 0x41, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB4, {0x00, 0x0D, 0x00, 0x00, 0x00 } }, + /* DPRX CAD Register Setting */ + { 2, 0x68, 0xB8, {0x8E, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8F, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x9A, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x9B, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x00, 0x0E, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x26, 0x02, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x01, 0x20, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC0, 0xF1, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC1, 0xF1, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC2, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC3, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC4, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC5, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC6, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0xC7, 0xF0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x0B, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x33, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x5B, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x10, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x38, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x60, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x15, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x3D, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x65, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x1A, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x42, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x6A, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x1F, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x47, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x6F, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x24, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x4C, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x74, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x29, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x51, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x79, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x2E, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x56, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x7E, 0x00, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x90, 0x10, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x91, 0x0F, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x92, 0xF6, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x93, 0x10, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x94, 0x0F, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x95, 0xF6, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x96, 0x10, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x97, 0x0F, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x98, 0xF6, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x99, 0x10, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x9A, 0x0F, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0x9B, 0xF6, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8A, 0x03, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x96, 0x03, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0xD1, 0x07, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xBB, {0xB0, 0x07, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8B, 0x04, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8C, 0x45, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x8D, 0x05, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x97, 0x04, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x98, 0xE0, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x99, 0x2E, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x80, {0x0E, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x14, 0x07, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x10, {0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Video size Related Settings for Non Present */ + { 5, 0x68, 0x01, {0x48, 0xB0, 0x04, 0x00, 0x00 } }, + { 5, 0x68, 0x29, {0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + /* eDP Settings for Link Training*/ + { 2, 0x68, 0xB6, {0x31, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x80, {0x01, 0x14, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x80, {0x02, 0x02, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB6, {0x08, 0x0B, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0xB8, {0x00, 0x1E, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x87, {0x00, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x50, {0x10, 0x00, 0x00, 0x9D, 0x00 } }, + { 5, 0x68, 0x00, {0x8C, 0x40, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x80, 0x02, 0x00, 0x00, 0x00 } }, + /* Link Training */ + { 2, 0x68, 0x82, {0x02, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x82, {0x03, 0xFF, 0x00, 0x00, 0x00 } }, + { 2, 0x68, 0x82, {0x04, 0xFF, 0x00, 0x00, 0x00 } }, + /* DSI Transition Time Setting for Non Preset */ + { 5, 0x68, 0x21, {0x54, 0x0D, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x21, {0x58, 0x06, 0x00, 0x2A, 0x00 } }, + { 5, 0x68, 0x21, {0x5C, 0x07, 0x00, 0x0E, 0x00 } }, + { 5, 0x68, 0x21, {0x60, 0x07, 0x00, 0x10, 0x00 } }, + { 5, 0x68, 0x21, {0x64, 0x10, 0x27, 0x00, 0x00 } }, + { 5, 0x68, 0x21, {0x68, 0x0E, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x21, {0x6C, 0x0A, 0x00, 0x0E, 0x00 } }, + { 5, 0x68, 0x21, {0x78, 0x0E, 0x00, 0x0D, 0x00 } }, + /* DSI Start */ + { 5, 0x68, 0x20, {0x7C, 0x81, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x20, {0x50, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x20, {0x1C, 0x01, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x20, {0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* GPIO for LCD control*/ + { 5, 0x68, 0x08, {0x04, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x80, 0x0F, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x84, 0x0F, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x84, 0x00, 0x00, 0x00, 0x00 } }, + { 5, 0x68, 0x00, {0x84, 0x0F, 0x00, 0x00, 0x00 } }, + /* DSI Hs Clock Mode */ + { 5, 0x68, 0x20, {0x50, 0x20, 0x00, 0x00, 0x00 } }, + /* LCD Initialization */ + { 5, 0x68, 0x22, {0xFC, 0x15, 0xBF, 0xA5, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x01, 0x00, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x8F, 0xA5, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x83, 0xAA, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x84, 0x11, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0xA9, 0x48, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x83, 0x00, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x84, 0x00, 0x81 } }, + { 5, 0x68, 0x22, {0xFC, 0x15, 0x8F, 0x00, 0x81 } }, + { 5, 0x68, 0x2A, {0x10, 0x10, 0x00, 0x04, 0x80 } }, + { 5, 0x68, 0x2A, {0x04, 0x01, 0x00, 0x00, 0x00 } }, + /* Check if eDP video is coming */ + { 5, 0x68, 0x01, {0x54, 0x01, 0x00, 0x00, 0x00 } }, +}; + +void mainboard_configure_edp_bridge(void); void *load_logo(size_t *logo_size);
#endif diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 91dfe3b..b600361 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -18,6 +18,9 @@
void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { + /* Configure the eDP bridge to eDP 1920 */ + mainboard_configure_edp_bridge(); + if (CONFIG(FSP1_1_DISPLAY_LOGO)) { size_t logo_len; void *logo = NULL;
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 1:
Uses CB:33225 (Braswell SMBus controller in i2c mode)
Hello Patrick Rudolph, Felix Held, David Hendricks, Philipp Deppenwiese, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33433
to look at the new patch set (#2).
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB first
BUG=N/A TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701 rev 0-2
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/facebook/fbg1701/mainboard.c M src/mainboard/facebook/fbg1701/mainboard.h M src/mainboard/facebook/fbg1701/ramstage.c 3 files changed, 328 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33433/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 4:
(2 comments)
looks good to me in general, but I'd like to have a bit easier to understand API that I wrote about in the other patch
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.h:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 21: number_of_databytes payload_length maybe?
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 23: u8 offset; /* register address [15:8] */ : u8 data[5]; /* First byte is register address [7:0] */ I'd merge those two. See my comments on the API on the Braswell I2C write patch.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.h:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 167: { 5, 0x00, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00 } }, maybe add a comment to this line, that this is for detecting the last entry of the array. Had to look twice to see that there's no bug in the code using this
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 315: { 5, 0x68, 0x01, {0x54, 0x01, 0x00, 0x00, 0x00 } }, the dummy entry in this array to detect the end of the array is missing here
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 4:
(3 comments)
Will implement comment.
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.h:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 21: number_of_databytes
payload_length maybe?
Done
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 23: u8 offset; /* register address [15:8] */ : u8 data[5]; /* First byte is register address [7:0] */
I'd merge those two. See my comments on the API on the Braswell I2C write patch.
Done
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 167: { 5, 0x00, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00 } },
maybe add a comment to this line, that this is for detecting the last entry of the array. […]
Done
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.h:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 25: } edp_data_t; There is some dislike about typedeffing structs, specially when they are for one-time use only.
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 27: static const edp_data_t mainboard_TC348860_InitTable[] = { Hmm.. allocation in .h file, doesn't this trigger defined-but-unused errors for files other than mainboard.c now?
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.c:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 25: void mainboard_configure_edp_bridge(void) Not sure why this was not placed in mainboard/ramstage.c instead?
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 27: edp_data_t *edptable; Target is a const array.
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 41: smbus_i2c_block_write(edptable->address, edptable->offset, The call should work fine with const arguments, also check return value for errors, in case you need to do retry.
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.h:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 25: } edp_data_t;
There is some dislike about typedeffing structs, specially when they are for one-time use only.
Will change to u8 table in ramstage.c
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 27: static const edp_data_t mainboard_TC348860_InitTable[] = {
Hmm.. allocation in . […]
No defined-but-unused. Will place table in ramstage.c
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 167: { 5, 0x00, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00 } },
Done
Done
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 315: { 5, 0x68, 0x01, {0x54, 0x01, 0x00, 0x00, 0x00 } },
the dummy entry in this array to detect the end of the array is missing here
When wrong with commit.
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.c:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 25: void mainboard_configure_edp_bridge(void)
Not sure why this was not placed in mainboard/ramstage. […]
Since it's mainboard specific it's placed in the mainboard.c file.
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.c:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 25: void mainboard_configure_edp_bridge(void)
Since it's mainboard specific it's placed in the mainboard.c file.
Done
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 27: edp_data_t *edptable;
Target is a const array.
Done
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 41: smbus_i2c_block_write(edptable->address, edptable->offset,
The call should work fine with const arguments, also check return value for errors, in case you need […]
Add check for error Did not use const argument for new patchset, cause do_i2c_block_write() is modify parameters.
Hello Patrick Rudolph, Felix Held, HAOUAS Elyes, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33433
to look at the new patch set (#5).
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB first
BUG=N/A TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701 rev 0-2
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/facebook/fbg1701/ramstage.c 1 file changed, 335 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33433/5
Hello Patrick Rudolph, Felix Held, HAOUAS Elyes, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33433
to look at the new patch set (#6).
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB first
BUG=N/A TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/facebook/fbg1701/ramstage.c 1 file changed, 335 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33433/6
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 7:
I have implement the comment on the items and upload new patchsets for the i2c Braswell and the mainboard using this support: CB:33433 CB:33225 CB:30800
Can you review these patches?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.h:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 25: } edp_data_t;
Will change to u8 table in ramstage. […]
It was just the use of 'typedef' there that caught my eye, it made perfect sense to have the structure defined.
Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, HAOUAS Elyes, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33433
to look at the new patch set (#8).
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB first.
BUG=N/A TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/facebook/fbg1701/ramstage.c 1 file changed, 332 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33433/8
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... File src/mainboard/facebook/fbg1701/mainboard.h:
https://review.coreboot.org/#/c/33433/4/src/mainboard/facebook/fbg1701/mainb... PS4, Line 25: } edp_data_t;
It was just the use of 'typedef' there that caught my eye, it made perfect sense to have the structu […]
Done
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 9: Code-Review+1
(3 comments)
https://review.coreboot.org/#/c/33433/9/src/mainboard/facebook/fbg1701/ramst... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/9/src/mainboard/facebook/fbg1701/ramst... PS9, Line 326: static const struct edp_data_t *edptable; No need for 'static' here.
https://review.coreboot.org/#/c/33433/9/src/mainboard/facebook/fbg1701/ramst... PS9, Line 329: CPLD_PCB_VERSION_BIT) < 7) Maybe you want to log with BIOS_DEBUG or BIOS_INFO the detected CPLD version?
https://review.coreboot.org/#/c/33433/9/src/mainboard/facebook/fbg1701/ramst... PS9, Line 342: (u8 *)&edptable->data[0]) < 0) Display will not be functional, log error with BIOS_ERR (or even higher). IMHO you should do a couple retries, but I leave it up to you to decide.
Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, HAOUAS Elyes, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33433
to look at the new patch set (#10).
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB first.
BUG=N/A TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/facebook/fbg1701/ramstage.c 1 file changed, 343 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33433/10
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 9:
(3 comments)
Implement comment
https://review.coreboot.org/#/c/33433/9/src/mainboard/facebook/fbg1701/ramst... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/9/src/mainboard/facebook/fbg1701/ramst... PS9, Line 326: static const struct edp_data_t *edptable;
No need for 'static' here.
Done
https://review.coreboot.org/#/c/33433/9/src/mainboard/facebook/fbg1701/ramst... PS9, Line 329: CPLD_PCB_VERSION_BIT) < 7)
Maybe you want to log with BIOS_DEBUG or BIOS_INFO the detected CPLD version?
Done
https://review.coreboot.org/#/c/33433/9/src/mainboard/facebook/fbg1701/ramst... PS9, Line 342: (u8 *)&edptable->data[0]) < 0)
Display will not be functional, log error with BIOS_ERR (or even higher). […]
Will add retry.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 11: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... PS11, Line 353: if (loops == 0) i'd print an error to console here. this case shouldn't happen, but when it happens there probably won't be working display output, so there should be an error message
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... PS11, Line 31: mainboard_TC348860_InitTable Please do not use CamelCase, use snake_case instead.
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... PS11, Line 175: mainboard_B101UAN08_InitTable Same here
Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, HAOUAS Elyes, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33433
to look at the new patch set (#12).
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB first.
BUG=N/A TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/facebook/fbg1701/ramstage.c 1 file changed, 344 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33433/12
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 12:
(3 comments)
Just upload new patchset. I expect all open items are solved and now ready for review/merge
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... PS11, Line 31: mainboard_TC348860_InitTable
Please do not use CamelCase, use snake_case instead.
Done
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... PS11, Line 175: mainboard_B101UAN08_InitTable
Same here
Done
https://review.coreboot.org/#/c/33433/11/src/mainboard/facebook/fbg1701/rams... PS11, Line 353: if (loops == 0)
i'd print an error to console here. […]
Done
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/#/c/33433/12/src/mainboard/facebook/fbg1701/rams... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/12/src/mainboard/facebook/fbg1701/rams... PS12, Line 31: static const struct edp_data_t tc348860_table[] = { Struct should be just 'edp_data', not 'edp_data_t'. I did not spot this earlier.
https://review.coreboot.org/#/c/33433/12/src/mainboard/facebook/fbg1701/rams... PS12, Line 355: return; Missing braces broke it !
Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, HAOUAS Elyes, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33433
to look at the new patch set (#14).
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB first.
BUG=N/A TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/facebook/fbg1701/ramstage.c 1 file changed, 345 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33433/14
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 14:
(2 comments)
https://review.coreboot.org/#/c/33433/12/src/mainboard/facebook/fbg1701/rams... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/12/src/mainboard/facebook/fbg1701/rams... PS12, Line 31: static const struct edp_data_t tc348860_table[] = {
Struct should be just 'edp_data', not 'edp_data_t'. I did not spot this earlier.
Done
https://review.coreboot.org/#/c/33433/12/src/mainboard/facebook/fbg1701/rams... PS12, Line 355: return;
Missing braces broke it !
Done
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 15: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 15: Code-Review+2
(2 comments)
Looks good. I added two comments. They are just "for the record", additional info I found. There's no need to update the patch.
https://review.coreboot.org/#/c/33433/15/src/mainboard/facebook/fbg1701/rams... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/15/src/mainboard/facebook/fbg1701/rams... PS15, Line 335: if (cpld_version < 7) : edptable = tc348860_table; : else : edptable = b101uan08_table; Looks like the TC348860 is a discrete eDP to MIPI DSI converter. The B101UAN08 looks like an eDP LCD panel, or am I wrong? I would comment on that.
https://review.coreboot.org/#/c/33433/15/src/mainboard/facebook/fbg1701/rams... PS15, Line 363: 1920 Looks like this board is part of an integrated device. I would guess that '1920' refers to the resolution of the integrated panel? I would use '1920x1200' instead.
(the '1200' should be correct, but please double check)
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 15:
(1 comment)
If there are no big concerns, I'll merge this patch in the current state tomorrow; the remaining nitpicks can be addressed in a follow-up patch
https://review.coreboot.org/#/c/33433/15/src/mainboard/facebook/fbg1701/rams... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/15/src/mainboard/facebook/fbg1701/rams... PS15, Line 363: 1920
Looks like this board is part of an integrated device. […]
maybe change this comment to the full resolution specification (1920x1200) in a separate patch on top of this one
Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs to be configured. Add mainboard_configure_edp_bridge() to program the controller. CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block write: <Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB first.
BUG=N/A TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335 Signed-off-by: Frans Hendriks fhendriks@eltan.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33433 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/facebook/fbg1701/ramstage.c 1 file changed, 345 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 91dfe3b..3903a64 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2018-2019 Facebook, Inc * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify @@ -13,11 +14,355 @@ * GNU General Public License for more details. */
+#include <arch/io.h> +#include <console/console.h> #include <soc/ramstage.h> +#include <soc/smbus.h> #include "mainboard.h" +#include "onboard.h" + +struct edp_data { + u8 payload_length; + u8 address; + /* data: reg[15:8],reg[7:0], data bytes starting with data[7:0] */ + u8 data[6]; +} __packed; + +static const struct edp_data tc348860_table[] = { + /* set eDP bridge to eDP 1920 */ + /* IO */ + { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } }, + /* Boot */ + { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } }, + { 6, 0x68, { 0x10, 0x08, 0x23, 0x00, 0x87, 0x02 } }, + { 6, 0x68, { 0x10, 0x0C, 0x19, 0x04, 0x00, 0x23 } }, + { 6, 0x68, { 0x10, 0x10, 0x06, 0x00, 0x67, 0x00 } }, + { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Internal */ + { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* eDP */ + { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } }, + /* DPRX */ + { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Video size */ + { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } }, + { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + /* eDP */ + { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } }, + { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } }, + /* Link Training */ + { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x21, 0x58, 0x09, 0x00, 0x28, 0x00 } }, + { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x0F, 0x00 } }, + { 6, 0x68, { 0x21, 0x64, 0x28, 0x23, 0x00, 0x00 } }, + { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } }, + /* DSI */ + { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* GPIO */ + { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + /* DSI clock */ + { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } }, + /* LCD init */ + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x85, 0x04, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x86, 0x08, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x05, 0x11, 0x00, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x05, 0x29, 0x00, 0x81 } }, + { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } }, + { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } }, + /* Check Video */ + { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } }, + /* End of table */ + { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, +}; + +static const struct edp_data b101uan08_table[] = { + /* set eDP bridge to eDP 1920 */ + /* IO Voltage Setting */ + { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } }, + /* Boot Settings */ + { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } }, + { 6, 0x68, { 0x10, 0x08, 0x22, 0x00, 0xA0, 0x02 } }, + { 6, 0x68, { 0x10, 0x0C, 0x50, 0x04, 0x00, 0x03 } }, + { 6, 0x68, { 0x10, 0x10, 0x10, 0x0D, 0x06, 0x01 } }, + { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Internal PCLK settings for Non Present or REFCLK=26MHz */ + { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } }, + /* DSI Clock setting for Non Preset or REFCLK=26MHz */ + { 6, 0x68, { 0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00 } }, + { 6, 0x68, { 0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00 } }, + { 6, 0x68, { 0x41, 0xC0, 0x30, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Additional Settng for eDP */ + { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } }, + /* DPRX CAD Register Setting */ + { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* Video size Related Settings for Non Present */ + { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } }, + { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + /* eDP Settings for Link Training*/ + { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } }, + { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } }, + /* Link Training */ + { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } }, + { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } }, + /* DSI Transition Time Setting for Non Preset */ + { 6, 0x68, { 0x21, 0x54, 0x0D, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x21, 0x58, 0x06, 0x00, 0x2A, 0x00 } }, + { 6, 0x68, { 0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00 } }, + { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x10, 0x00 } }, + { 6, 0x68, { 0x21, 0x64, 0x10, 0x27, 0x00, 0x00 } }, + { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00 } }, + { 6, 0x68, { 0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00 } }, + /* DSI Start */ + { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + /* GPIO for LCD control*/ + { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } }, + { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + /* DSI Hs Clock Mode */ + { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } }, + /* LCD Initialization */ + { 6, 0x68, { 0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0x00, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x00, 0x81 } }, + { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81 } }, + { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } }, + { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } }, + /* Check if eDP video is coming */ + { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } }, + /* End of table */ + { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, +}; + +static void mainboard_configure_edp_bridge(void) +{ + u8 cpld_version; + const struct edp_data *edptable; + unsigned int loops; + int status; + + cpld_version = (inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> + CPLD_PCB_VERSION_BIT; + printk(BIOS_DEBUG, "CPLD version: %x\n", cpld_version); + if (cpld_version < 7) + edptable = tc348860_table; + else + edptable = b101uan08_table; + + /* reset bridge */ + outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT); + outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT); + + /* set eDP bridge to eDP 1920 */ + while (edptable->payload_length) { + loops = 5; + do { + status = smbus_i2c_block_write(edptable->address, + edptable->payload_length, + (u8 *)&edptable->data[0]); + } while (--loops && (status < 0)); + + if (loops == 0) { + printk(BIOS_ERR, "Writing eDP bridge failed!\n"); + return; + } + edptable++; + }; +}
void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { + /* Configure the eDP bridge to eDP 1920 */ + mainboard_configure_edp_bridge(); + if (CONFIG(FSP1_1_DISPLAY_LOGO)) { size_t logo_len; void *logo = NULL;
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33433 )
Change subject: mainboard/facebook/fbg1701: Configure TC358860 eDP to MIPI controller ......................................................................
Patch Set 16:
(2 comments)
Have upload a new patchset solving the comments on this patchset.
The new patchset: https://review.coreboot.org/c/coreboot/+/33736
https://review.coreboot.org/#/c/33433/15/src/mainboard/facebook/fbg1701/rams... File src/mainboard/facebook/fbg1701/ramstage.c:
https://review.coreboot.org/#/c/33433/15/src/mainboard/facebook/fbg1701/rams... PS15, Line 335: if (cpld_version < 7) : edptable = tc348860_table; : else : edptable = b101uan08_table;
Looks like the TC348860 is a discrete eDP to MIPI DSI converter. […]
All revsions contains the TC348660. Will used LCD Panel type for table name
https://review.coreboot.org/#/c/33433/15/src/mainboard/facebook/fbg1701/rams... PS15, Line 363: 1920
maybe change this comment to the full resolution specification (1920x1200) in a separate patch on to […]
Have removed the comment with resolution. Now only resolution info at top of tables.
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Angel Pons (Code Review) -
Felix Held (Code Review)
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Frans Hendriks (Code Review)
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Kyösti Mälkki (Code Review)