Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87223?usp=email )
Change subject: mb/intel/ptlrvp: Synchronize codebase with fatcat ......................................................................
mb/intel/ptlrvp: Synchronize codebase with fatcat
This commit imports changes from mb/google/fatcat to mb/intel/ptlrvp as of commit coreboot codebase 010cfa28421bd52f1f16798ddf5b2116ea3f7f7a ("doc/internals/devicetree_language: multiple segment groups supported").
Here is the list of imported commits: - 9495063993e ("mainboard/google/fatcat: Fix SMBIOS Processor upgrade info") - 27f3427f4a1 ("mb/google/fatcat/var/fatcat: Update GSPI0 CS pin for FPS") - c41af2d43c4 ("mb/google/fatcat/var/fatcat: Update THC Interrupt for Touchpad Development") - d19dd192dbe ("mb/google/fatcat: Add PTL-U Fast VMode Voltage Regulator settings") - b5dea9fa999 ("mb/google/fatcat/var/francka: Add Write Protect GPIO to cros_gpios") - ef80ccbc436 ("mb/google/fatcat: Disable EC software sync for Microchip EC") - 9f39d6ec5e9 ("mb/google/fatcat: Enable HAVE_SLP_S0_GATE for felino and francka") - eb85dfae1f2 ("mb/google/fatcat: Configure GPIO_SLP_S0_GATE for francka and felino") - 0fc2422e88d ("mb/google/fatcat: Implement S0ix hooks aka `MS0X` method") - 1fa5ab805bb ("mb/google/fatcat: Remove unnecessary CNVi core variables settings") - 5c0340349ec ("mb/google/fatcat: Rationalize Wi-Fi and Bluetooth combinations") - 275beb93db8 ("mb/google/fatcat: Conditionally check for barrel charger") - e9b020f02e3 ("mb/google/fatcat: Allow board-specific FSP-M UPD override") - 3a88eb8cb6c ("mb/google/fatcat: Enable HDA SDI based on FW config") - 0ac2058dbee ("mb/google/fatcat: Increase sagv_freq_mhz for work point #1 to #3") - 6e529e7c061 ("mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad")
Overall, these patches aim to improve the configuration, performance, and compatibility of the Google Fatcat mainboard across various aspects, including processor upgrade support, peripheral integration, power management, and audio functionality.
Change-Id: Ie27763a367d8d53c64ad78d26909f1068af3c819 Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/mainboard/intel/ptlrvp/Kconfig M src/mainboard/intel/ptlrvp/mainboard.c M src/mainboard/intel/ptlrvp/romstage.c M src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb M src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h M src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c M src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk M src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c M src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c M src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb M src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c 12 files changed, 282 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/87223/1
diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig index 73e170d..0b2afc6 100644 --- a/src/mainboard/intel/ptlrvp/Kconfig +++ b/src/mainboard/intel/ptlrvp/Kconfig @@ -3,6 +3,7 @@ config BOARD_INTEL_PTLRVP_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select CPU_INTEL_SOCKET_OTHER select DRIVERS_GFX_GENERIC select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -46,7 +47,6 @@ select DRIVERS_INTEL_ISH select DRIVER_INTEL_ISH_HAS_MAIN_FW select DRIVERS_INTEL_USB4_RETIMER - select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS select MEMORY_SOLDERDOWN select SOC_INTEL_COMMON_BLOCK_HDA_VERB @@ -60,6 +60,7 @@ select BOARD_INTEL_BASEBOARD_PTLRVP select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_MAX98357A + select DRIVERS_INTEL_TOUCH
config BOARD_INTEL_PTLRVP select BOARD_INTEL_MODEL_PTLRVP @@ -74,7 +75,7 @@
config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC_MEC select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/intel/ptlrvp/mainboard.c b/src/mainboard/intel/ptlrvp/mainboard.c index f514eb9..e14c5ac 100644 --- a/src/mainboard/intel/ptlrvp/mainboard.c +++ b/src/mainboard/intel/ptlrvp/mainboard.c @@ -58,6 +58,32 @@ */ }
+static void mainboard_generate_s0ix_hook(void) +{ + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + { + if (CONFIG(HAVE_SLP_S0_GATE)) + acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE); + variant_generate_s0ix_hook(S0IX_ENTRY); + } + acpigen_write_else(); + { + if (CONFIG(HAVE_SLP_S0_GATE)) + acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE); + variant_generate_s0ix_hook(S0IX_EXIT); + } + acpigen_write_if_end(); +} + +static void mainboard_fill_ssdt(const struct device *dev) +{ + acpigen_write_scope("\_SB"); + acpigen_write_method_serialized("MS0X", 1); + mainboard_generate_s0ix_hook(); + acpigen_write_method_end(); /* Method */ + acpigen_write_scope_end(); /* Scope */ +} + static void mainboard_dev_init(struct device *dev) { mainboard_ec_init(); @@ -66,6 +92,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; }
struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c index b6e3681..1c52971 100644 --- a/src/mainboard/intel/ptlrvp/romstage.c +++ b/src/mainboard/intel/ptlrvp/romstage.c @@ -4,6 +4,7 @@ #include <ec/intel/board_id.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <soc/soc_chip.h> #include <string.h>
/* @@ -17,6 +18,11 @@ /* Nothing to do */ }
+__weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd) +{ + /* Nothing to do */ +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; @@ -45,4 +51,7 @@ die("Unknown board id = 0x%x\n", board_id); break; } + + /* Override FSP-M UPD per board if required. */ + variant_update_soc_memory_init_params(memupd); } diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h index 5a59f1f..d44ef98 100644 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h @@ -4,6 +4,7 @@ #define __BASEBOARD_VARIANTS_H__
#include <chip.h> +#include <fsp/api.h> #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> @@ -30,6 +31,7 @@ void variant_get_spd_info(struct mem_spd *spd_info); int variant_memory_sku(void); bool variant_is_half_populated(void); +void variant_update_soc_memory_init_params(FSPM_UPD *memupd); void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
enum s0ix_entry { diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb index 2cf249f9..9ef8451 100644 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb +++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb @@ -36,13 +36,13 @@ register "sagv_freq_mhz[0]" = "2400" register "sagv_gear[0]" = "GEAR_4"
- register "sagv_freq_mhz[1]" = "3200" + register "sagv_freq_mhz[1]" = "4800" register "sagv_gear[1]" = "GEAR_4"
- register "sagv_freq_mhz[2]" = "6000" + register "sagv_freq_mhz[2]" = "6400" register "sagv_gear[2]" = "GEAR_4"
- register "sagv_freq_mhz[3]" = "6400" + register "sagv_freq_mhz[3]" = "6800" register "sagv_gear[3]" = "GEAR_4"
# Enable s0ix @@ -62,6 +62,23 @@ # Enable Energy Reporting register "pch_pm_energy_report_enable" = "true"
+ # As per document 813278, the Intel PTL-U 15W SoC supports + # Fast V-Mode (FVM) on cores (IA), Graphics (GT), and System + # Agent (SA). The ICC Limit is represented in 1/4 A + # increments, i.e., a value of 400 = 100A. + # IA VR configuration + register "enable_fast_vmode[VR_DOMAIN_IA]" = "true" + register "cep_enable[VR_DOMAIN_IA]" = "true" + register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "252" # 63A + # GT VR configuration + register "enable_fast_vmode[VR_DOMAIN_GT]" = "true" + register "cep_enable[VR_DOMAIN_GT]" = "true" + register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "152" # 38A + # SA VR configuration + register "enable_fast_vmode[VR_DOMAIN_SA]" = "true" + register "cep_enable[VR_DOMAIN_SA]" = "true" + register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "152" # 38A + # Enable CNVi BT register "cnvi_bt_core" = "true"
@@ -81,7 +98,6 @@ register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "true" - register "pch_hda_sdi_enable" = "{ true, false }"
device domain 0 on device ref dtt on end diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h index 5a77e4e..b169d35 100644 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h +++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h @@ -13,5 +13,6 @@ #define EC_SYNC_IRQ 0 /* WP signal to PCH */ #define GPIO_PCH_WP 0 +#define GPIO_SLP_S0_GATE 0 /* Not Connected */
#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c index 030b587..b284372 100644 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c +++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c @@ -53,7 +53,7 @@ void baseboard_devtree_update(void) { /* Don't optimize the power limit if booting with barrel attached */ - if (google_chromeec_is_barrel_charger_present()) + if (CONFIG(BOARD_INTEL_MODEL_FATCAT) && google_chromeec_is_barrel_charger_present()) return;
if (!google_chromeec_is_battery_present()) diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk index eb361df..b9f1fd1 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk @@ -5,5 +5,5 @@ romstage-y += memory.c romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c -ramstage-$(CONFIG_FW_CONFIG) += variant.c +romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c index 9419caf..afd8a63 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c @@ -351,6 +351,8 @@ PAD_NC(GPP_E17, NONE), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_NC(GPP_E18, NONE), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), };
static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = { @@ -370,6 +372,8 @@ PAD_NC(GPP_E17, NONE), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), };
static const struct pad_config touchscreen_thc_i2c_enable_pads[] = { @@ -388,7 +392,10 @@ /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ PAD_NC(GPP_E17, NONE), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ - PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), + /* NOTE: this SPI INT NF is also used in THC-I2C mode */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), };
static const struct pad_config touchscreen_gspi_enable_pads[] = { @@ -407,7 +414,9 @@ /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ - PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT) + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), };
static const struct pad_config touchscreen_thc_spi_enable_pads[] = { @@ -428,13 +437,21 @@ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), };
static const struct pad_config touchpad_thc_i2c_enable_pads[] = { - /* GPP_F12: NF1: thc_i2c1_scl */ + /* GPP_F12: NF1: THC_I2C1_SCL */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* GPP_F13: NF1: thc_i2c1_sda */ + /* GPP_F13: NF1: THC_I2C1_SDA */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: this SPI INT NF is also used in THC-I2C mode */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), };
static const struct pad_config touchpad_lpss_i2c_enable_pads[] = { @@ -442,8 +459,11 @@ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), - /* GPP_A13: TCH_PAD_INT_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), };
static const struct pad_config touchpad_i2c_disable_pads[] = { @@ -451,8 +471,21 @@ PAD_NC(GPP_F12, NONE), /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_NC(GPP_F13, NONE), - /* GPP_A13: TCH_PAD_INT_N */ - PAD_NC(GPP_A13, NONE), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_NC(GPP_F18, NONE), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), +}; + +static const struct pad_config thc0_enable_wake[] = { + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC0, NONE, PLTRST, LEVEL, NONE), +}; + +static const struct pad_config thc1_enable_wake[] = { + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC1, NONE, PLTRST, LEVEL, NONE), };
static const struct pad_config ish_disable_pads[] = { @@ -477,6 +510,7 @@ PAD_NC(GPP_C15, NONE), /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ PAD_CFG_GPO(GPP_D01, 1, DEEP), + PAD_NC(GPP_E17, NONE), /* FIXME: b/390031369 * use dedicated GPIO PIN for codec enable * when FPS is enabled. @@ -487,7 +521,6 @@ PAD_NC(GPP_F14, NONE), PAD_NC(GPP_F15, NONE), PAD_NC(GPP_F16, NONE), - PAD_NC(GPP_F18, NONE), };
static const struct pad_config fp_enable_pads[] = { @@ -495,6 +528,8 @@ PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), /* GPP_D01: FPS_SOC_INT_L */ PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT), + /* GPP_E17: GSPI0A_CS0 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), /* GPP_E19: FPMCU_PWREN */ PAD_CFG_GPO(GPP_E19, 1, DEEP), /* GPP_E20: FPMCU_FW_UPDATE */ @@ -505,8 +540,6 @@ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), /* GPP_F16: GPSI0A_CLK */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), - /* GPP_F18: GSPI0A_CS0 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8), };
static const struct pad_config pre_mem_fp_enable_pads[] = { @@ -556,6 +589,8 @@
void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { + const struct soc_intel_pantherlake_config *config = config_of_soc(); + if (!fw_config_is_provisioned()) { printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); return; @@ -618,23 +653,31 @@ else GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
- if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) + if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) + } else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads); - else + if (config->thc_wake_on_touch[1]) + GPIO_PADBASED_OVERRIDE(padbased_table, thc1_enable_wake); + } else { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads); + }
- if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C))) + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) + if (config->thc_wake_on_touch[0]) + GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake); + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads); - else + if (config->thc_wake_on_touch[0]) + GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake); + } else { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads); + }
if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE))) GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads); @@ -644,8 +687,26 @@ /* NOTE: disable PEG (x8 slot) and x4 slot wake for now */ GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
- if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) - GPIO_CONFIGURE_PADS(fp_enable_pads); - else - GPIO_CONFIGURE_PADS(fp_disable_pads); + /* + * *=========================================================================* + * | userage | GPP_E17 | + * *=========================================================================* + * | touchscreen in THC-SPI (with rework) | NF3: THC HID-SPI CS0 | + * *---------------------------------------*---------------------------------* + * | touchscreen in gSPI (with rework) | NF5: GSPI0 CS0 | + * *---------------------------------------*---------------------------------* + * | FPS present (without rework) | NF5: GSPI0 CS0 | + * *---------------------------------------*---------------------------------* + * + * NOTE: 1. CBI selecting TS THC-SPI or GSPI mode implies TS rework is applied for the board. + * 2. CBI selecting TS THC-SPI or TS GSPI with FSP present is invalid case. + */ + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)) || + fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) { + /* board has TS SPI rework and not FPS support */ + } else if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) { + GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads); + } } diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c index 1accd4d..9531065 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c @@ -217,8 +217,6 @@ /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ /* THC NOTE: use GPO instead of GPO for THC0 Rst */ PAD_CFG_GPO(GPP_E16, 1, DEEP), - /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), /* GPP_E21: I2C_PMC_PD_INT_N */ @@ -262,6 +260,9 @@ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* GPP_F17: Not used */ PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), /* GPP_F19: GPP_PRIVACY_LED_CAM2 */ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */ @@ -414,6 +415,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME), CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME), CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME), };
DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb index cb4c21a..c6a63c3 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb @@ -77,7 +77,7 @@ register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework @@ -317,13 +317,66 @@ device ref iaa off end
device ref thc0 on + register "thc_wake_on_touch[0]" = "true" probe TOUCHSCREEN TOUCHSCREEN_THC_SPI probe TOUCHSCREEN TOUCHSCREEN_THC_I2C # THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled. probe TOUCHPAD TOUCHPAD_THC_I2C + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_I2C_MODE" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "enable_delay_ms" = "2" + register "enable_off_delay_ms" = "2" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_ELAN" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_0_i2c_elan on + probe TOUCHSCREEN TOUCHSCREEN_THC_I2C + end + end + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_SPI_MODE" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "enable_delay_ms" = "2" + register "enable_off_delay_ms" = "2" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "2" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_ELAN" + register "soc_hidspi.write_mode" = "HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI" + register "soc_hidspi.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_0_spi_elan on + probe TOUCHSCREEN TOUCHSCREEN_THC_SPI + end + end end device ref thc1 on + register "thc_wake_on_touch[1]" = "true" probe TOUCHPAD TOUCHPAD_THC_I2C + chip drivers/intel/touch + register "name" = "INTEL_THC1_NAME" + register "mode" = "THC_HID_I2C_MODE" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_HYNITRON" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_1_i2c_hynitron on end + end end
device ref tbt_pcie_rp0 on end @@ -444,7 +497,10 @@ register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)" - device ref usb2_port8 on end + device ref usb2_port8 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port 1"" @@ -570,9 +626,16 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion device generic 0 on end end end # CNVi + + device ref cnvi_bluetooth on + probe WIFI WIFI_CNVI_6 + probe WIFI WIFI_CNVI_7 + end + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. device ref i2c0 on end @@ -801,9 +864,11 @@ end # I2C3 device ref i2c4 on chip drivers/i2c/hid - register "generic.hid" = ""ELAN6918"" + register "generic.hid" = ""ELAN9048"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)" + # NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb. + register "generic.wake" = "GPE0_DW2_18" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" register "generic.reset_delay_ms" = "20" @@ -821,8 +886,9 @@ chip drivers/i2c/hid register "generic.hid" = ""HFW68H"" register "generic.desc" = ""Hynitron TOUCHPAD"" - register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)" - register "generic.wake" = "GPE0_DW0_13" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)" + # NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c. + register "generic.wake" = "GPE0_DW0_18" register "generic.uid" = "5" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c index c7aa7aa..5ba7683 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpigen.h> #include <baseboard/variants.h> +#include <fsp/api.h> #include <fw_config.h> #include <sar.h> +#include <soc/gpio_soc_defs.h> +#include <drivers/intel/touch/chip.h>
const char *get_wifi_sar_cbfs_filename(void) { @@ -12,8 +14,6 @@
void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) { - config->cnvi_wifi_core = false; - config->cnvi_bt_core = false; /* CNVi */ if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) || fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) { @@ -27,4 +27,60 @@ config->cnvi_bt_audio_offload = true; } } + + /* Touchscreen and touchpad WOT support: + * +===================+==================+=================+============================+ + * | touchsreen | touchpad | PMC_GPE0_DW0 | WOT | + * +===================+==================+==============================================+ + * | THC-SPI/THC-I2C | LPSS-I2C | GPP_F | TS, TP | + * +-------------------+------------------+----------------------------------------------+ + * | THC-SPI/THC-I2C | not used or | GPP_A (default) | TS | + * | | with WOT disabled| | | + * +-------------------+------------------+----------------------------------------------+ + * | THC-SPI/THC-I2C | THC-I2C | GPP_A (default) | TS, TP | + * +-------------------+------------------+----------------------------------------------+ + * | LPSS-SPI/LPSS-I2C | LPSS-I2C | GPP_F | TS via PMC_GPE0_DW2: GPP_E,| + * | | | | TP | + * +-------------------+------------------+----------------------------------------------+ + * | LPSS-SPI/LPSS-I2C | not used or | GPP_A (default) | TS via PMC_GPE0_DW2: GPP_E | + * | | with WOT disabled| | | + * +-------------------+------------------+----------------------------------------------+ + * | not used | not used or | GPP_A (default) | NA | + * | with WOT disabled | with WOT disabled| | | + * +===================+==================+=================+============================+ + */ + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) { + config->thc_mode[0] = THC_HID_I2C_MODE; + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) { + config->thc_mode[0] = THC_HID_SPI_MODE; + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) { + config->serial_io_gspi_mode[PchSerialIoIndexGSPI0] = PchSerialIoPci; + } + + if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) { + /* touchpad: GPP_F18: GPE0_DW0_18 */ + if (config->thc_wake_on_touch[1]) + config->pmc_gpe0_dw0 = GPP_F; + } else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) { + config->thc_mode[1] = THC_HID_I2C_MODE; + + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) + /* When THC0 is only enabled due to THC1 is enabled, we force THC0 + * to I2C mode so that kernel THC I2C driver will find it and put + * THC0 to low power state because no connected device is found. + */ + config->thc_mode[0] = THC_HID_I2C_MODE; + } +} + +void variant_update_soc_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; + + /* HDA Audio */ + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) { + printk(BIOS_INFO, "Overriding HDA SDI lanes.\n"); + m_cfg->PchHdaSdiEnable[0] = true; + m_cfg->PchHdaSdiEnable[1] = false; + } }
-
Jérémy Compostella (Code Review)