[S] Change in coreboot[main]: mainboard: Introduce BIOS_SIZE

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Chen, Gang C, David Hendricks, Jincheng Li, Jonathan Zhang, Shuo Liu, TangYiwei.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81320?usp=email )

Change subject: mainboard: Introduce BIOS_SIZE
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Patch Set 1:

(2 comments)

Patchset:

PS1: 
Shuo, can you provide a memory map for this? This seems very different
to all prior Intel silicon. For instance where are your APICs when you
can have >16MiB cacheable directly below 4G?

File src/mainboard/Kconfig:

https://review.coreboot.org/c/coreboot/+/81320/comment/2681bd8b_77bde4a7 :
PS1, Line 257: config BIOS_SIZE_KB_16384
             : 	bool "16384 KB (16 MB)"
             : 	help
             : 	  Choose this option if your BIOS region is 16384 KB (16 MB).
             : 
             : config BIOS_SIZE_KB_32768
             : 	bool "32768 KB (32 MB)"
             : 	help
             : 	  Choose this option if your BIOS region is 32768 KB (32 MB).
             : 
             : config BIOS_SIZE_KB_49512
             : 	bool "49512 KB (48 MB)"
             : 	help
             : 	  Choose this option if your BIOS region is 49512 KB (48 MB).
             : 
             : # Map the config names to the value
             : config BIOS_SIZE
             : 	hex
             : 	default 0x01000000 if BIOS_SIZE_KB_16384
             : 	default 0x02000000 if BIOS_SIZE_KB_32768
             : 	default 0x03000000 if BIOS_SIZE_KB_49512
             : 	default 0x01000000
> Drop the Kconfig variables. […]

I believe this is actually a case for `CACHE_ROM_BASE`/`CACHE_ROM_SIZE`
from `include/cpu/x86/mtrr.h`.