Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46705 )
Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ......................................................................
mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, TODO.
Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb 3 files changed, 57 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46705/1
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index b7c6fe5..4f34f7d 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -16,10 +16,6 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
- # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - device cpu_cluster 0 on device lapic 0 on end end @@ -27,33 +23,40 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal + +# chip soc/intel/broadwell/pch + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 - LAN + device pci 1c.3 on end # PCIe Port #4 - WiFi + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal +# end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae7..237e697 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell
- # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - device domain 0 on - device pci 1c.2 on end # PCIe Port #3 - LAN +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device pci 1c.2 on end # PCIe Port #3 - LAN +# end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d03..b9b29cd 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell
- # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device domain 0 on - device pci 1d.0 on end # USB2 EHCI +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device pci 1d.0 on end # USB2 EHCI +# end end end
Angel Pons has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/46705 )
Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ......................................................................
mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb 3 files changed, 57 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46705/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46705
to look at the new patch set (#4).
Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ......................................................................
mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb 3 files changed, 57 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46705/4
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46705
to look at the new patch set (#5).
Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ......................................................................
mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb 3 files changed, 57 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46705/5
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46705
to look at the new patch set (#7).
Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ......................................................................
mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb 3 files changed, 57 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46705/7
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46705 )
Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ......................................................................
Patch Set 13: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46705 )
Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ......................................................................
Patch Set 13: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46705 )
Change subject: mb/purism/librem_bdw: Prepare devicetree for PCH split ......................................................................
mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb 3 files changed, 57 insertions(+), 50 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index b7c6fe5..4f34f7d 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -16,10 +16,6 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
- # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - device cpu_cluster 0 on device lapic 0 on end end @@ -27,33 +23,40 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal + +# chip soc/intel/broadwell/pch + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 - LAN + device pci 1c.3 on end # PCIe Port #4 - WiFi + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal +# end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae7..237e697 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell
- # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - device domain 0 on - device pci 1c.2 on end # PCIe Port #3 - LAN +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device pci 1c.2 on end # PCIe Port #3 - LAN +# end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d03..b9b29cd 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell
- # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device domain 0 on - device pci 1d.0 on end # USB2 EHCI +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device pci 1d.0 on end # USB2 EHCI +# end end end
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Michael Niewöhner (Code Review)