Change in coreboot[master]: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46462 )
Change subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` ......................................................................
mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Singer felixsinger@posteo.net Reviewed-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 51 files changed, 2 insertions(+), 116 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Frans Hendriks: Looks good to me, approved
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 294ae44..561bd6f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -28,9 +28,6 @@ register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000c1641"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0"
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index d6f29a2..57acd33 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -18,9 +18,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 8f256ad..e8827bf 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -19,9 +19,6 @@ .tdp_pl2_override = 30, }"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1"
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index bb11d06..15ab7ef 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -29,9 +29,6 @@ # "Intel SpeedStep Technology" register "eist_enable" = "1"
- # "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index b7aa11d..4713589 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -136,9 +136,6 @@ register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1"
- # Enable Speed Shift Technology support - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 775c548..bbb63bc 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -134,9 +134,6 @@ register "gpio_pm[3]" = "0" register "gpio_pm[4]" = "0"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index aa6af87..de3b5ca 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -40,7 +40,6 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1"
- register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index a2550bb..519e53b 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -227,7 +227,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- register "speed_shift_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 9c11e80..703ef5b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -305,7 +305,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_psyspl2 = 90, .psys_pmax = 120, diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 12312e9..2dfb71f 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -30,9 +30,6 @@ register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 10ad029..cdd83df 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -29,8 +29,6 @@ register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" - # Enable Speed Shift Technology support - register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" # Enable DPTF diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 9f9d951..3797fb0 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -59,7 +59,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1"
- register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 0dc9131..0b3d6c0 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -246,7 +246,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 167bd03..d408f9e 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -266,8 +266,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- register "speed_shift_enable" = "1" - register "tcc_offset" = "3" # TCC of 97C register "power_limits_config" = "{ .psys_pmax = 101, diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ed21492..b7d171b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -268,7 +268,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 0a29601..ab1588a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -54,8 +54,6 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1"
- # Set speed_shift_enable to 1 to enable P-States, and 0 to disable - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 18, diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 591e0fb..2334a17 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -225,7 +225,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- register "speed_shift_enable" = "1" # PL2 override 18W for AML-Y register "power_limits_config" = "{ .tdp_pl2_override = 18, diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index b3570d7..c698755 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -247,7 +247,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b1d9a36..3ff9b30 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -29,7 +29,6 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1"
- register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e1ee6c9..17d0127 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -32,7 +32,6 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1"
- register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b76f627..2a62505 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -230,9 +230,6 @@ register "DdiPort3Ddc" = "0" register "DdiPort4Ddc" = "0"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1"
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 818f32f..7305501 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -13,8 +13,6 @@ register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration - # Enable Speed Shift Technology/HWP support - register "speed_shift_enable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index e100598..1110bc1 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -60,9 +60,6 @@ register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index bf7aa1e..4202314 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -57,9 +57,6 @@ register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 0b40a5c..12b1c47 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -43,9 +43,6 @@ register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable S0ix register "s0ix_enable" = "0"
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 49303da..1215628 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -152,9 +152,6 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index a1c32c9..e8c6e8f 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -152,9 +152,6 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index b9aec37..61a5e70 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -122,9 +122,6 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 8de089d..e17c8b7 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 3afff45..07afb7b 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -17,9 +17,6 @@ register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index a25cb8c..5c64326 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -14,9 +14,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # FSP Configuration register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 09ab258..de93c99 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,9 +115,6 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 25c2293..4078894 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -119,9 +119,6 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1"
diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 357f8fa..ef1f0d4 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -2,8 +2,6 @@
chip soc/intel/skylake
- register "speed_shift_enable" = "1" - register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index d47eca8..911690f 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -30,9 +30,6 @@ register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0"
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 071fc5f..04e6774 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -126,8 +126,6 @@ # Thermal register "tcc_offset" = "6" # TCC of 94C
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1"
# Disable S0ix register "s0ix_enable" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 2a4b1e9..e6e748a 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -17,8 +17,6 @@ register "gen3_dec" = "0x000c03e1" register "gen4_dec" = "0x001c02e1"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" register "eist_enable" = "1"
# Disable DPTF diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 23c5712..2c73280 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -37,9 +37,6 @@ register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0"
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb index 497a4cc..2050332 100644 --- a/src/mainboard/purism/librem_whl/devicetree.cb +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -24,9 +24,6 @@ .tdp_pl2_override = 28, }"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index edf1333..4f8ceb6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -19,9 +19,6 @@ register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000c1641"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0"
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 505e9a4..cca8838 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -4,7 +4,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "RMT" = "0" - register "speed_shift_enable" = "1"
register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 5a2fc01..3c9d968 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -4,7 +4,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "RMT" = "0" - register "speed_shift_enable" = "1"
register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index dd0e520..e7b26dc 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -3,9 +3,6 @@ register "deep_s5_enable_ac" = "0" register "deep_s5_enable_dc" = "0"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # FSP Configuration register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 277570e..84c0312 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -19,9 +19,6 @@ .tdp_pl2_override = 30, }"
- # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1"
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index aaf03f5..428fd4d 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -185,8 +185,6 @@ uint8_t HeciEnabled; /* PL2 Override value in Watts */ uint32_t tdp_pl2_override; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 69a2cf2..7f428a2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -261,8 +261,6 @@ /* Enables support for Teton Glacier hybrid storage device */ uint8_t TetonGlacierMode;
- /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable VR specific mailbox command * 00b - no VR specific cmd sent * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 5037147..26d0f0d 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -149,8 +149,6 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 386e775..e1b697e 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -169,8 +169,7 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; + /* Enable VR specific mailbox command * 00b - no VR specific cmd sent * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 4410de9..5e90530 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -149,8 +149,6 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2584d5d..41482f1 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -461,8 +461,7 @@ */ u8 HeciEnabled; u8 PmTimerDisabled; - /* Intel Speed Shift Technology */ - u8 speed_shift_enable; + /* * Enable VR specific mailbox command * 000b - Don't Send any VR command diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fb6cda0..f752b5f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -271,9 +271,6 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled;
- /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable;
-
Patrick Georgi (Code Review)