Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46678 )
Change subject: nb/intel/haswell/finalize.c: Drop obsolete SA PM lock ......................................................................
nb/intel/haswell/finalize.c: Drop obsolete SA PM lock
This register had a lock bit on Sandy Bridge, but does not on Haswell. Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot. Therefore, remove the write to this bit, because it has no effect.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I382a6d69233ced5af069767eb61b56741ed665be Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46678/1
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index bff0344..ca10146 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -18,7 +18,6 @@ pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ MCHBAR32_OR(REQLIM, 1UL << 31);
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46678 )
Change subject: nb/intel/haswell/finalize.c: Drop obsolete SA PM lock ......................................................................
Patch Set 2: Code-Review+2
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46678
to look at the new patch set (#4).
Change subject: nb/intel/haswell/finalize.c: Drop obsolete SA PM lock ......................................................................
nb/intel/haswell/finalize.c: Drop obsolete SA PM lock
This register had a lock bit on Sandy Bridge, but does not on Haswell. Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot. Therefore, remove the write to this bit, because it has no effect.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I382a6d69233ced5af069767eb61b56741ed665be Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46678/4
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46678 )
Change subject: nb/intel/haswell/finalize.c: Drop obsolete SA PM lock ......................................................................
nb/intel/haswell/finalize.c: Drop obsolete SA PM lock
This register had a lock bit on Sandy Bridge, but does not on Haswell. Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot. Therefore, remove the write to this bit, because it has no effect.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I382a6d69233ced5af069767eb61b56741ed665be Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46678 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 0 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index bff0344..ca10146 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -18,7 +18,6 @@ pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ MCHBAR32_OR(REQLIM, 1UL << 31);
-
Angel Pons (Code Review) -
Nico Huber (Code Review)