Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison c...
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33913
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience
Reorder lines to make it more similar to i.e. buildOpts.c of Lenovo G505S. This is needed to improve the convenience of comparison during the debugging.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 39 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33913/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 30c0699..93d7738 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -28,7 +28,6 @@ #include <stdlib.h> #include <AGESA.h>
-#define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
#define INSTALL_G34_SOCKET_SUPPORT FALSE @@ -43,6 +42,7 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE @@ -66,7 +66,7 @@ #define BLDOPT_REMOVE_SRAT FALSE //TRUE #define BLDOPT_REMOVE_SLIT FALSE //TRUE #define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE @@ -86,28 +86,14 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT #define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 +#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
@@ -138,34 +124,52 @@ #define BLDCFG_SCRUB_L3_RATE 0 #define BLDCFG_SCRUB_IC_RATE 0 #define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD FALSE #define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. + +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) #endif
-#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT + +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define OPTION_GFX_INIT_SVIEW FALSE + #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
+#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + /* Process the options... * This file include MUST occur AFTER the user option selection settings */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 1:
(9 comments)
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 133: #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the line over 96 characters
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 134: // core for C-state entry requests. A value line over 96 characters
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 134: // core for C-state entry requests. A value code indent should use tabs where possible
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 135: // of 0 in this field specifies that the core line over 96 characters
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 135: // of 0 in this field specifies that the core code indent should use tabs where possible
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 136: // does not trap any IO addresses for C-state entry. line over 96 characters
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 136: // does not trap any IO addresses for C-state entry. code indent should use tabs where possible
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 137: // Values greater than 0xFFF8 results in undefined behavior. line over 96 characters
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 137: // Values greater than 0xFFF8 results in undefined behavior. code indent should use tabs where possible
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 1:
am1i-a/buildOpts.c patch series [1/8] : 1st = CB:33913 <-- you are here ; 2nd = CB:33914 , 3rd = CB:33915 , 4th = CB:33916 , 5th = CB:33917 , 6th = CB:33918 , 7th = CB:33919 , 8th = CB:33920
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 1:
(2 comments)
I am not convinced
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 31: : supported socket are at the same 'bloc'
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 143: please, why this is removed?
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 31: :
supported socket are at the same 'bloc'
I brought it closer to #ifdef's using this #define, but could return it back if you would like. Sadly can't do it immediately because of hard drive problems :(
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 143:
please, why this is removed?
Other board didn't have it and omitting "ul" does not cause any difference. Perhaps I should've separated it in its' own commit, but this is so tiny... Should I do this?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/#/c/33913/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 143:
Other board didn't have it and omitting "ul" does not cause any difference. […]
I have no idea if you should or not. it was just a question
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33913
to look at the new patch set (#2).
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience
Reorder lines to make it more similar to i.e. buildOpts.c of Lenovo G505S. This is needed to improve the convenience of comparison during the debugging.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 39 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33913/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 2:
(9 comments)
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 132: #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the line over 96 characters
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 133: // core for C-state entry requests. A value line over 96 characters
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 133: // core for C-state entry requests. A value code indent should use tabs where possible
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 134: // of 0 in this field specifies that the core line over 96 characters
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 134: // of 0 in this field specifies that the core code indent should use tabs where possible
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 135: // does not trap any IO addresses for C-state entry. line over 96 characters
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 135: // does not trap any IO addresses for C-state entry. code indent should use tabs where possible
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 136: // Values greater than 0xFFF8 results in undefined behavior. line over 96 characters
https://review.coreboot.org/#/c/33913/2/src/mainboard/asus/am1i-a/buildOpts.... PS2, Line 136: // Values greater than 0xFFF8 results in undefined behavior. code indent should use tabs where possible
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 3:
(9 comments)
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 132: #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 133: // core for C-state entry requests. A value line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 133: // core for C-state entry requests. A value code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 134: // of 0 in this field specifies that the core line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 134: // of 0 in this field specifies that the core code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 135: // does not trap any IO addresses for C-state entry. line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 135: // does not trap any IO addresses for C-state entry. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 136: // Values greater than 0xFFF8 results in undefined behavior. line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/3/src/mainboard/asus/am1i-a/b... PS3, Line 136: // Values greater than 0xFFF8 results in undefined behavior. code indent should use tabs where possible
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 4:
(9 comments)
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 132: #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 133: // core for C-state entry requests. A value line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 133: // core for C-state entry requests. A value code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 134: // of 0 in this field specifies that the core line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 134: // of 0 in this field specifies that the core code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 135: // does not trap any IO addresses for C-state entry. line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 135: // does not trap any IO addresses for C-state entry. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 136: // Values greater than 0xFFF8 results in undefined behavior. line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/4/src/mainboard/asus/am1i-a/b... PS4, Line 136: // Values greater than 0xFFF8 results in undefined behavior. code indent should use tabs where possible
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 5:
(9 comments)
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 132: #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 133: // core for C-state entry requests. A value line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 133: // core for C-state entry requests. A value code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 134: // of 0 in this field specifies that the core line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 134: // of 0 in this field specifies that the core code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 135: // does not trap any IO addresses for C-state entry. line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 135: // does not trap any IO addresses for C-state entry. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 136: // Values greater than 0xFFF8 results in undefined behavior. line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/5/src/mainboard/asus/am1i-a/b... PS5, Line 136: // Values greater than 0xFFF8 results in undefined behavior. code indent should use tabs where possible
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33913/1/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/33913/1/src/mainboard/asus/am1i-a/b... PS1, Line 31: define INSTALL_FT3_SOCKET_SUPPORT TRUE : #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
I brought it closer to #ifdef's using this #define, but could return it back if you would like. […]
Already done. I hoped that this change series (CB:33913 - CB:33920) will help me to get a 1866MHz CL9 RAM working at least on 1600MHz CL9 speed instead of coreboot's 1333MHz CL9, but sadly it turned out to be not enough...
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33913/1/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/33913/1/src/mainboard/asus/am1i-a/b... PS1, Line 143: ul
I have no idea if you should or not. […]
Already done. I hoped that this change series (CB:33913 - CB:33920) will help me to get a 1866MHz CL9 RAM working at least on 1600MHz CL9 speed instead of coreboot's 1333MHz CL9, but sadly it turned out to be not enough...
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 6:
(9 comments)
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 120: #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 121: // core for C-state entry requests. A value line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 121: // core for C-state entry requests. A value code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 122: // of 0 in this field specifies that the core line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 122: // of 0 in this field specifies that the core code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 123: // does not trap any IO addresses for C-state entry. line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 123: // does not trap any IO addresses for C-state entry. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 124: // Values greater than 0xFFF8 results in undefined behavior. line over 96 characters
https://review.coreboot.org/c/coreboot/+/33913/6/src/mainboard/asus/am1i-a/b... PS6, Line 124: // Values greater than 0xFFF8 results in undefined behavior. code indent should use tabs where possible
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33913
to look at the new patch set (#7).
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience
Reorder lines to make it more similar to i.e. buildOpts.c of Lenovo G505S. This is needed to improve the convenience of comparison during the debugging.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 39 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33913/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 7: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG@9 PS7, Line 9: i.e. Remove, it isn't grammatically correct
It also makes the line short enough to fit in 72 chars
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG@10 PS7, Line 10: This is needed to improve the convenience of comparison during the debugging. This improves diff results, which is convenient for debugging.
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG@11 PS7, Line 11: Maybe test this with BUILD_TIMELESS=1 to make sure it is just a cosmetic change:
make BUILD_TIMELESS=1 -j$(nproc)
Build and compare (diff -s -q) the coreboot.rom that results before and after applying this change, they should be identical.
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG@9 PS7, Line 9: i.e.
Remove, it isn't grammatically correct […]
Done.
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG@10 PS7, Line 10: This is needed to improve the convenience of comparison during the debugging.
This improves diff results, which is convenient for debugging.
Done.
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG@11 PS7, Line 11:
Maybe test this with BUILD_TIMELESS=1 to make sure it is just a cosmetic change: […]
Identical SHA256 :)
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33913
to look at the new patch set (#8).
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience
Reorder lines to make it more similar to buildOpts.c of Lenovo G505S. This improves diff results, which is convenient for debugging.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 39 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33913/8
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG@11 PS7, Line 11:
Identical SHA256 :)
Alright, please mention this in the commit message:
Tested with BUILD_TIMELESS=1, hashes do not change.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 8: Code-Review+1
Hello build bot (Jenkins), Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33913
to look at the new patch set (#9).
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience
Reorder lines to make it more similar to buildOpts.c of Lenovo G505S. This improves diff results, which is convenient for debugging. Tested with BUILD_TIMELESS=1, hashes do not change.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 39 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33913/9
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33913/7//COMMIT_MSG@11 PS7, Line 11:
Alright, please mention this in the commit message: […]
Done
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
Patch Set 9: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/33913 )
Change subject: mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience ......................................................................
mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience
Reorder lines to make it more similar to buildOpts.c of Lenovo G505S. This improves diff results, which is convenient for debugging. Tested with BUILD_TIMELESS=1, hashes do not change.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33913 Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 39 insertions(+), 36 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Michał Żygowski: Looks good to me, approved
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 46e2a1d..5889592 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include <AGESA.h>
-#define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
#define INSTALL_G34_SOCKET_SUPPORT FALSE @@ -30,7 +29,7 @@ #define INSTALL_FT1_SOCKET_SUPPORT FALSE #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - +#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE @@ -54,7 +53,7 @@ #define BLDOPT_REMOVE_SRAT FALSE //TRUE #define BLDOPT_REMOVE_SLIT FALSE //TRUE #define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE @@ -74,28 +73,14 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT #define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 +#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
@@ -126,34 +111,52 @@ #define BLDCFG_SCRUB_L3_RATE 0 #define BLDCFG_SCRUB_IC_RATE 0 #define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD FALSE #define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. + +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) #endif
-#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT + +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define OPTION_GFX_INIT_SVIEW FALSE + #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
+#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + /* Process the options... * This file include MUST occur AFTER the user option selection settings */
-
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