Change in coreboot[master]: soc/intel/tigerlake: update fsp_param setting based on latest baseline
Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40349 )
Change subject: soc/intel/tigerlake: update fsp_param setting based on latest baseline ......................................................................
soc/intel/tigerlake: update fsp_param setting based on latest baseline
Merge the recent change from other platform(ICL/JSL).
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 33 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/40349/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c old mode 100644 new mode 100755 index ff6d3a9..13c9139 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> @@ -85,14 +86,21 @@ /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get();
- params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - + /* Check if IGD is present and fill Graphics init param accordingly */ dev = pcidev_path_on_root(SA_DEVFN_IGD); if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0;
+ /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->SkipMpInit = 0; + } else { + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + } + params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = 0x09000000; @@ -127,7 +135,7 @@ get_l1_substate_control(config->PcieRpL1Substates[i]);
/* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -142,7 +150,7 @@ params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
/* SATA */ - dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); + dev = pcidev_path_on_root(PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -156,7 +164,7 @@ }
/* LAN */ - dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c old mode 100644 new mode 100755 index 9933200..ac44ceb --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -20,8 +20,17 @@ uint32_t mask = 0; const struct device *dev;
+ dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (!dev || !dev->enabled) { + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; /* Set IGD stolen size to 60MB. */ m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; @@ -60,22 +69,19 @@ /* Disable BIOS Guard */ m_cfg->BiosGuard = 0;
- /* UART Debug Log */ + /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : - DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; - m_cfg->PcdIsaSerialUartBase = 0x0; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO;
- /* - * Skip IGD initialization in FSP if device - * is disable in devicetree.cb. - */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) - m_cfg->InternalGfx = 0; - else - m_cfg->InternalGfx = 0x1; + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } + + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
/* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH);
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40349
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: update fsp_param setting based on latest baseline ......................................................................
soc/intel/tigerlake: update fsp_param setting based on latest baseline
Merge the recent change from other platform(ICL/JSL).
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 33 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/40349/2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40349 )
Change subject: soc/intel/tigerlake: update fsp_param setting based on latest baseline ......................................................................
Patch Set 2: Code-Review+1
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Ravishankar Sarawadi, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40349
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Merge the recent change from other platforms ......................................................................
soc/intel/tigerlake: Merge the recent change from other platforms
Merge the recent change from other platform(ICL/JSL). - Update SKpMpInit setting - Update APIs for getting dev info - Update IGD related setting - Update debug interface setting
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 33 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/40349/3
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Ravishankar Sarawadi, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40349
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Merge the recent change from other platforms ......................................................................
soc/intel/tigerlake: Merge the recent change from other platforms
Merge the recent change from other platform(ICL/JSL). - Update SKpMpInit setting - Update APIs for getting dev info - Update IGD related setting - Update debug interface setting
BRANCH=none TEST=build and boot ripto/volteer
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 33 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/40349/4
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40349 )
Change subject: soc/intel/tigerlake: Merge the recent change from other platforms ......................................................................
Patch Set 4: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40349 )
Change subject: soc/intel/tigerlake: Merge the recent change from other platforms ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40349/4/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/40349/4/src/soc/intel/tigerlake/rom... PS4, Line 30: /* Set IGD stolen size to 60MB. */ : m_cfg->IgdDvmt50PreAlloc = 0xFE; indentation?
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Ravishankar Sarawadi, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40349
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Merge the recent change from other platforms ......................................................................
soc/intel/tigerlake: Merge the recent change from other platforms
Merge the recent change from other platform(ICL/JSL). - Update SKpMpInit setting - Update APIs for getting dev info - Update IGD related setting - Update debug interface setting
BRANCH=none TEST=build and boot ripto/volteer
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 35 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/40349/5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40349 )
Change subject: soc/intel/tigerlake: Merge the recent change from other platforms ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/40349/4/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/40349/4/src/soc/intel/tigerlake/rom... PS4, Line 30: /* Set IGD stolen size to 60MB. */ : m_cfg->IgdDvmt50PreAlloc = 0xFE;
indentation?
Done
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40349 )
Change subject: soc/intel/tigerlake: Merge the recent change from other platforms ......................................................................
Patch Set 5: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40349 )
Change subject: soc/intel/tigerlake: Merge the recent change from other platforms ......................................................................
soc/intel/tigerlake: Merge the recent change from other platforms
Merge the recent change from other platform(ICL/JSL). - Update SKpMpInit setting - Update APIs for getting dev info - Update IGD related setting - Update debug interface setting
BRANCH=none TEST=build and boot ripto/volteer
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/40349 Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 35 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, but someone else must approve Srinidhi N Kaushik: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 78cfb9f..5acad20 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> @@ -86,14 +87,21 @@ /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get();
- params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - + /* Check if IGD is present and fill Graphics init param accordingly */ dev = pcidev_path_on_root(SA_DEVFN_IGD); if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0;
+ /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->SkipMpInit = 0; + } else { + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + } + params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = 0x09000000; @@ -144,7 +152,7 @@ config->PcieRpAdvancedErrorReporting[i]; } /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -159,7 +167,7 @@ params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
/* SATA */ - dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); + dev = pcidev_path_on_root(PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -173,7 +181,7 @@ }
/* LAN */ - dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 9933200..6056b4b 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -20,8 +20,17 @@ uint32_t mask = 0; const struct device *dev;
- /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (!dev || !dev->enabled) { + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; @@ -60,22 +69,19 @@ /* Disable BIOS Guard */ m_cfg->BiosGuard = 0;
- /* UART Debug Log */ + /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : - DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; - m_cfg->PcdIsaSerialUartBase = 0x0; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO;
- /* - * Skip IGD initialization in FSP if device - * is disable in devicetree.cb. - */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) - m_cfg->InternalGfx = 0; - else - m_cfg->InternalGfx = 0x1; + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } + + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
/* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH);
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Caveh Jalali (Code Review) -
Patrick Georgi (Code Review)
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Srinidhi N Kaushik (Code Review)
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Wonkyu Kim (Code Review)