Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47043 )
Change subject: sb/intel/lynxpoint/lpc.c: Update LPC programming sequences ......................................................................
sb/intel/lynxpoint/lpc.c: Update LPC programming sequences
Change-Id: I98327e011fe764c9f53c80754e9fd5adc4ee29ee Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 6 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47043/1
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 373bafc..ee0dc53 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -283,9 +283,7 @@ outl(reg32, pmbase + 0x04);
/* Clear magic status bits to prevent unexpected wake */ - reg32 = RCBA32(0x3310); - reg32 |= (1 << 4) | (1 << 5) | (1 << 0); - RCBA32(0x3310) = reg32; + RCBA32_OR(0x3310, (1 << 4) | (1 << 5) | (1 << 0));
reg16 = RCBA16(0x3f02); reg16 &= ~0xf; @@ -307,9 +305,7 @@
RCBA32_AND_OR(0x232c, ~1, 0);
- RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); - RCBA32_OR(0x1100, 0x00000100); - RCBA32_OR(0x1100, 0x0000003f); + RCBA32_OR(0x1100, 0x0000c13f);
RCBA32_AND_OR(0x2320, ~0x60, 0x10);
@@ -340,6 +336,8 @@ RCBA32(0x3a24) = 0x01010101; RCBA32(0x3a30) = 0x01010101;
+ pci_and_config32(dev, 0xac, ~(1 << 21)); + RCBA32_OR(0x0410, 0x00000003); RCBA32_OR(0x2618, 0x08000000); RCBA32_OR(0x2300, 0x00000002); @@ -360,8 +358,6 @@ RCBA32(0x3a80) = 0x05145005; RCBA32(0x3a84) = 0x00001005;
- pci_or_config32(dev, 0xac, 1 << 21); - pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); pch_iobp_update(0xED000118, ~0, 0x00c00000); pch_iobp_update(0xED000120, ~0, 0x00240000); @@ -410,7 +406,8 @@ u16 reg16;
/* DMI */ - RCBA32_AND_OR(0x2234, ~0, 0xf); + RCBA32_OR(0x2234, 0xf); + reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~((1 << 11) | (1 << 14)); reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13);