[S] Change in coreboot[main]: sb/intel/bd82x6x/early_usb: Add USB TX/RX gains

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78829?usp=email )

Change subject: sb/intel/bd82x6x/early_usb: Add USB TX/RX gains
......................................................................

sb/intel/bd82x6x/early_usb: Add USB TX/RX gains

Describe the USB 'current' settings based on MRC.bin that converts
the USB trace length to a predefined register value.
MRC.bin decides which setting to use based on the PC type, mobile
or desktop, and the trace length.

Tested:	Lenovo X220 still boots.

Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78829
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/southbridge/intel/bd82x6x/early_usb.c
M src/southbridge/intel/bd82x6x/pch.h
2 files changed, 19 insertions(+), 6 deletions(-)

Approvals:
  Arthur Heymans: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 974c190..35bfeca 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -16,26 +16,27 @@
    	/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
    	/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
    };
-	const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51,
-				 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357,
-				 0x20000353 };
+	const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT,
+				 USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f,
+				 USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353 };
    int i;

/* Unlock registers.  */
    write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN);

for (i = 0; i < 14; i++) {
-		if (portmap[i].enabled && !pch_is_mobile() && portmap[i].current == 0) {
+		if (portmap[i].enabled && !pch_is_mobile() &&
+		    currents[portmap[i].current] == USBIR_TXRX_GAIN_MOBILE_LOW) {
    		/*
    		 * Note for developers: You can fix this by re-running autoport on
    		 * vendor firmware and then updating portmap currents accordingly.
    		 * If that is not possible, another option is to choose a non-zero
    		 * current setting. In either case, please test all the USB ports.
    		 */
-			printk(BIOS_ERR, "%s: USB%02d: current setting of 0 is an invalid setting for desktop!\n",
+			printk(BIOS_ERR, "%s: USB%02d: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!\n",
    		       __func__, i);

-			RCBA32(USBIR0 + 4 * i) = currents[1];
+			RCBA32(USBIR0 + 4 * i) = USBIR_TXRX_GAIN_DEFAULT;
    	} else {
    		RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current];
    	}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 88c8df5c..040b477 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -382,6 +382,18 @@
 #define USBIR12		0x3530	/* 32bit */
 #define USBIR13		0x3534	/* 32bit */

+/* Up to 5" onboard trace length */
+#define USBIR_TXRX_GAIN_MOBILE_LOW	0x20000153
+
+/* Up to 6" onboard trace length */
+#define USBIR_TXRX_GAIN_DESKTOP_LOW	0x20000F53
+
+/* Up to 14" onboard trace length, up to 8" on wires */
+#define USBIR_TXRX_GAIN_DEFAULT		0x20000f57
+
+/* Up to 10" onboard trace length, up to 15" on wires */
+#define USBIR_TXRX_GAIN_HIGH		0x2000055B
+
 /* Miscellaneous Control Register */
 #define MISCCTL		0x3590	/* 32bit */
 /* USB Port Disable Override */