Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: haswell: Set up Root Complex topology ......................................................................
haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/lpc.c 3 files changed, 95 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/1
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index baa4f32..e6dfe3a 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -91,6 +91,11 @@ #define GLBIOTLBINV (1 << 1) #define GLBCTXTINV (1 << 0)
+/* Device 0:1.0 PCI configuration space (PCIe Graphics Attach) */ +#define PEG_DCAP2 0xc4 /* 32bit */ +#define PEG_ESD 0x144 /* 32bit */ +#define PEG_LE1D 0x150 /* 32bit */ +#define PEG_LE1A 0x158 /* 64bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */
@@ -144,6 +149,10 @@ #define EPLE1A 0x058 /* 64bit */ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ +#define EPLE3D 0x070 /* 32bit */ +#define EPLE3A 0x078 /* 64bit */ +#define EPLE4D 0x080 /* 32bit */ +#define EPLE4A 0x088 /* 64bit */
#define PORTARB 0x100 /* 256bit */
@@ -169,6 +178,8 @@ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */
+#define DMIESD 0x044 /* 32bit */ + #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ #define DMILE2D 0x060 /* 32bit */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4311710..25ed828 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -453,12 +453,80 @@ DMIBAR8(0xd34) = 0x44; }
+static void northbridge_topology_init(void) +{ + struct device *dev; + + /* Set the CID1 EP Port Root Topology */ + EPBAR32(EPESD) = (1 << 16); + + EPBAR32(EPLE1D) = (1 << 16) | 1; + EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + + dev = pcidev_on_root(1, 0); + if (dev && dev->enabled) { + + EPBAR32(EPLE2A) = 0x8000; + EPBAR32(EPLE2D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + dev = pcidev_on_root(1, 1); + if (dev && dev->enabled) { + + EPBAR32(EPLE3A) = 0x9000; + EPBAR32(EPLE3D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + dev = pcidev_on_root(1, 2); + if (dev && dev->enabled) { + + EPBAR32(EPLE4A) = 0xa000; + EPBAR32(EPLE4D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + /* Set the CID1 DMI Port Root Topology */ + DMIBAR32(DMIESD) = (1 << 16) | 1; + + DMIBAR32(DMILE1D) = (2 << 16) | 1; + DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + + DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; + DMIBAR32(DMILE2D) = (1 << 16) | 1; + + /* Program RO and Write-Once Registers */ + DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1); + DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP); +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair;
- if (!CONFIG(INTEL_LYNXPOINT_LP)) + if (!CONFIG(INTEL_LYNXPOINT_LP)) { northbridge_dmi_init(); + northbridge_topology_init(); + }
/* Enable Power Aware Interrupt Routing. */ pair = MCHBAR8(INTRDIRCTL); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3298b0..85fab4d 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -19,6 +19,7 @@ #include "nvs.h" #include "pch.h" #include <acpi/acpigen.h> +#include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> @@ -500,6 +501,18 @@ RCBA32_OR(0x21a8, 0x3); }
+static void pch_topology_init(void) +{ + /* Set component id to 2 for southbridge, northbridge has id 1 */ + RCBA32(ESD) = (2 << 16); + + /* Set target port number and target component id of the northbridge */ + RCBA32(ULD) = (1 << 24) | (1 << 16); + + /* Set target RCRB base address, i.e. DMIBAR */ + RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; +} + static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); @@ -546,6 +559,8 @@ pch_set_acpi_mode();
pch_fixups(dev); + + pch_topology_init(); }
static void pch_lpc_add_mmio_resources(struct device *dev)
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43744
to look at the new patch set (#2).
Change subject: haswell: Set up Root Complex topology ......................................................................
haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/lpc.c 3 files changed, 95 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: haswell: Set up Root Complex topology ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43744/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/43744/2/src/northbridge/intel/haswe... PS2, Line 471: dev = pcidev_on_root(1, 0); : if (dev && dev->enabled) { : : EPBAR32(EPLE2A) = 0x8000; : EPBAR32(EPLE2D) = (1 << 16) | 1; : : pci_write_config32(dev, PEG_ESD, (1 << 16)); : pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); : pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); : : /* Read and write to lock register */ : pci_or_config32(dev, PEG_DCAP2, 0); : } : : dev = pcidev_on_root(1, 1); : if (dev && dev->enabled) { : : EPBAR32(EPLE3A) = 0x9000; : EPBAR32(EPLE3D) = (1 << 16) | 1; : : pci_write_config32(dev, PEG_ESD, (1 << 16)); : pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); : pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); : : /* Read and write to lock register */ : pci_or_config32(dev, PEG_DCAP2, 0); : } : : dev = pcidev_on_root(1, 2) loop?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: haswell: Set up Root Complex topology ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43744/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/43744/2/src/northbridge/intel/haswe... PS2, Line 471: dev = pcidev_on_root(1, 0); : if (dev && dev->enabled) { : : EPBAR32(EPLE2A) = 0x8000; : EPBAR32(EPLE2D) = (1 << 16) | 1; : : pci_write_config32(dev, PEG_ESD, (1 << 16)); : pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); : pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); : : /* Read and write to lock register */ : pci_or_config32(dev, PEG_DCAP2, 0); : } : : dev = pcidev_on_root(1, 1); : if (dev && dev->enabled) { : : EPBAR32(EPLE3A) = 0x9000; : EPBAR32(EPLE3D) = (1 << 16) | 1; : : pci_write_config32(dev, PEG_ESD, (1 << 16)); : pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); : pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); : : /* Read and write to lock register */ : pci_or_config32(dev, PEG_DCAP2, 0); : } : : dev = pcidev_on_root(1, 2)
loop?
I can't use the EPLExA/EPLExD macros then. But what I can do is put it inside a function
Hello build bot (Jenkins), Nico Huber, Arthur Heymans, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43744
to look at the new patch set (#3).
Change subject: haswell: Set up Root Complex topology ......................................................................
haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/lpc.c 3 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: haswell: Set up Root Complex topology ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43744/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/43744/2/src/northbridge/intel/haswe... PS2, Line 471: dev = pcidev_on_root(1, 0); : if (dev && dev->enabled) { : : EPBAR32(EPLE2A) = 0x8000; : EPBAR32(EPLE2D) = (1 << 16) | 1; : : pci_write_config32(dev, PEG_ESD, (1 << 16)); : pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); : pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); : : /* Read and write to lock register */ : pci_or_config32(dev, PEG_DCAP2, 0); : } : : dev = pcidev_on_root(1, 1); : if (dev && dev->enabled) { : : EPBAR32(EPLE3A) = 0x9000; : EPBAR32(EPLE3D) = (1 << 16) | 1; : : pci_write_config32(dev, PEG_ESD, (1 << 16)); : pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); : pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); : : /* Read and write to lock register */ : pci_or_config32(dev, PEG_DCAP2, 0); : } : : dev = pcidev_on_root(1, 2)
I can't use the EPLExA/EPLExD macros then. […]
Done
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: haswell: Set up Root Complex topology ......................................................................
Removed Verified+1 by build bot (Jenkins) no-reply@coreboot.org
Hello build bot (Jenkins), Nico Huber, Maxim Polyakov, Tristan Corrick, Tim Wawrzynczak, Arthur Heymans, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43744
to look at the new patch set (#7).
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
nb/intel/haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c 2 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 7:
This change is ready for review.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 7: Code-Review+1
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43744/8/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/43744/8/src/northbridge/intel/haswe... PS8, Line 82: #define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + x)) Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43744/8/src/northbridge/intel/haswe... PS8, Line 120: #define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + x)) Macros with complex values should be enclosed in parentheses
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 8: Code-Review+1
Might be good to test on a haswell-lp device?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 8:
Patch Set 8: Code-Review+1
Might be good to test on a haswell-lp device?
Yes, I'd appreciate if you could do this. I have a HSW-LP board but it's a very WIP port.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... PS9, Line 82: #define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + x)) Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... PS9, Line 120: #define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + x)) Macros with complex values should be enclosed in parentheses
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 9:
Patch Set 8:
Patch Set 8: Code-Review+1
Might be good to test on a haswell-lp device?
Yes, I'd appreciate if you could do this. I have a HSW-LP board but it's a very WIP port.
Arthur, did you get a chance to test on haswell-lp?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 9: Code-Review+2
Tested on Google/Peppy.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... PS9, Line 506: 0x8000 This is the same as PCI_DEV(0, 1, 0)
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... PS9, Line 507: 0x9000 PCI_DEV(0, 1, 1)
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... PS9, Line 508: 0xa000 PCI_DEV(0, 1, 2)
Hello build bot (Jenkins), Nico Huber, Maxim Polyakov, Tristan Corrick, Tim Wawrzynczak, Arthur Heymans, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43744
to look at the new patch set (#10).
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
nb/intel/haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/registers/epbar.h 3 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/10
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... PS9, Line 506: 0x8000
This is the same as PCI_DEV(0, 1, 0)
Ack
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... PS9, Line 507: 0x9000
PCI_DEV(0, 1, 1)
Ack
https://review.coreboot.org/c/coreboot/+/43744/9/src/northbridge/intel/haswe... PS9, Line 508: 0xa000
PCI_DEV(0, 1, 2)
Ack
Hello build bot (Jenkins), Nico Huber, Maxim Polyakov, Tristan Corrick, Tim Wawrzynczak, Arthur Heymans, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43744
to look at the new patch set (#11).
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
nb/intel/haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/registers/epbar.h 3 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/11
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43744/11/src/northbridge/intel/hasw... File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/43744/11/src/northbridge/intel/hasw... PS11, Line 70: #define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + (x))) Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43744/11/src/northbridge/intel/hasw... PS11, Line 81: #define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + (x))) Macros with complex values should be enclosed in parentheses
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 12: Code-Review+2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43744/12/src/northbridge/intel/hasw... File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/43744/12/src/northbridge/intel/hasw... PS12, Line 70: #define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + (x))) Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43744/12/src/northbridge/intel/hasw... PS12, Line 81: #define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + (x))) Macros with complex values should be enclosed in parentheses
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43744/13/src/northbridge/intel/hasw... File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/43744/13/src/northbridge/intel/hasw... PS13, Line 70: #define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + (x))) Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/43744/13/src/northbridge/intel/hasw... PS13, Line 81: #define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + (x))) Macros with complex values should be enclosed in parentheses
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: nb/intel/haswell: Set up Root Complex topology ......................................................................
nb/intel/haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43744 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/registers/epbar.h 3 files changed, 79 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 4bcaaa7..b160f83 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -20,6 +20,14 @@
#include "registers/host_bridge.h"
+/* Device 0:1.0 PCI configuration space (PCIe Graphics) */ + +#define PEG_DCAP2 0xc4 /* 32bit */ + +#define PEG_ESD 0x144 /* 32bit */ +#define PEG_LE1D 0x150 /* 32bit */ +#define PEG_LE1A 0x158 /* 64bit */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */ @@ -59,6 +67,7 @@ #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) +#define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + (x)))
#include "registers/epbar.h"
@@ -69,6 +78,7 @@ #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + (x)))
#include "registers/dmibar.h"
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 5619d95..9cf564f 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -498,12 +498,77 @@ } }
+static void northbridge_topology_init(void) +{ + const u32 eple_a[3] = { EPLE2A, EPLE3A, EPLE4A }; + const u32 eple_d[3] = { EPLE2D, EPLE3D, EPLE4D }; + + u32 reg32; + + /* Set the CID1 Egress Port 0 Root Topology */ + reg32 = EPBAR32(EPESD); + reg32 &= ~(0xff << 16); + reg32 |= 1 << 16; + EPBAR32(EPESD) = reg32; + + reg32 = EPBAR32(EPLE1D); + reg32 &= ~(0xff << 16); + reg32 |= 1 | (1 << 16); + EPBAR32(EPLE1D) = reg32; + EPBAR64(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + + for (unsigned int i = 0; i <= 2; i++) { + const struct device *const dev = pcidev_on_root(1, i); + + if (!dev || !dev->enabled) + continue; + + EPBAR64(eple_a[i]) = (u64)PCI_DEV(0, 1, i); + + reg32 = EPBAR32(eple_d[i]); + reg32 &= ~(0xff << 16); + reg32 |= 1 | (1 << 16); + EPBAR32(eple_d[i]) = reg32; + + pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1A + 4, 0); + pci_update_config32(dev, PEG_LE1D, ~(0xff << 16), (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + /* Set the CID1 DMI Port Root Topology */ + reg32 = DMIBAR32(DMIESD); + reg32 &= ~(0xff << 16); + reg32 |= 1 << 16; + DMIBAR32(DMIESD) = reg32; + + reg32 = DMIBAR32(DMILE1D); + reg32 &= ~(0xffff << 16); + reg32 |= 1 | (2 << 16); + DMIBAR32(DMILE1D) = reg32; + DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + + DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; + reg32 = DMIBAR32(DMILE2D); + reg32 &= ~(0xff << 16); + reg32 |= 1 | (1 << 16); + DMIBAR32(DMILE2D) = reg32; + + /* Program RO and Write-Once Registers */ + DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1); + DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP); +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair;
init_egress(); northbridge_dmi_init(); + northbridge_topology_init();
/* Enable Power Aware Interrupt Routing. */ pair = MCHBAR8(INTRDIRCTL); diff --git a/src/northbridge/intel/haswell/registers/epbar.h b/src/northbridge/intel/haswell/registers/epbar.h index 963cead..699a2ba 100644 --- a/src/northbridge/intel/haswell/registers/epbar.h +++ b/src/northbridge/intel/haswell/registers/epbar.h @@ -20,5 +20,9 @@ #define EPLE1A 0x058 /* 64bit */ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ +#define EPLE3D 0x070 /* 32bit */ +#define EPLE3A 0x078 /* 64bit */ +#define EPLE4D 0x080 /* 32bit */ +#define EPLE4A 0x088 /* 64bit */
#endif /* __HASWELL_REGISTERS_EPBAR_H__ */
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