Change in coreboot[master]: arch/x86: Add a common romstage entry

[Arthur Heymans (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Patrick Rudolph, Felix Held.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55067 )

Change subject: arch/x86: Add a common romstage entry
......................................................................

arch/x86: Add a common romstage entry

It might be possible to have this used for more than x86, but that
will be for a later commit.

Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans 
---
M src/arch/x86/Makefile.inc
M src/cpu/intel/car/romstage.c
M src/drivers/amd/agesa/romstage.c
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/example/min86/romstage.c
7 files changed, 13 insertions(+), 35 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55067/1

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3949e3a..957beed 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -141,6 +141,7 @@
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)

romstage-y += assembly_entry.S
+romstage-y += romstage.c
 romstage-y += boot.c
 romstage-y += post.c
 romstage-y += gdt_init.S
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 63ddd74..d88ed95 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -8,6 +8,7 @@
 #include <commonlib/helpers.h>
 #include <program_loading.h>
 #include <timestamp.h>
+#include <romstage_common.h>
 #include <security/vboot/vboot_common.h>

/* If we do not have a constrained _car_stack region size, use the
@@ -16,7 +17,7 @@

static struct postcar_frame early_mtrrs;

-static void romstage_main(void)
+void romstage_main(void)
 {
    int i;
    const int num_guards = 64;
@@ -57,13 +58,3 @@
    prepare_and_run_postcar(&early_mtrrs);
    /* We do not return here. */
 }
-
-asmlinkage void car_stage_entry(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	/* Assumes the hardware was set up during the bootblock */
-	console_init();
-
-	romstage_main();
-}
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 9b11a15..6255970 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -13,6 +13,7 @@
 #include <smp/node.h>
 #include <string.h>
 #include <timestamp.h>
+#include <romstage_common.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>

@@ -31,17 +32,13 @@
  */
 static void ap_romstage_main(void);

-static void romstage_main(void)
+void romstage_main(void)
 {
    struct postcar_frame pcf;
    struct sysinfo romstage_state;
    struct sysinfo *cb = &romstage_state;
    int cbmem_initted = 0;

-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-
    fill_sysinfo(cb);

board_BeforeAgesa(cb);
@@ -97,11 +94,6 @@
    halt();
 }

-asmlinkage void car_stage_entry(void)
-{
-	romstage_main();
-}
-
 void *cbmem_top_chipset(void)
 {
    /* Top of CBMEM is at highest usable DRAM address below 4GiB. */
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index d3e1bd7..e60deac 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <romstage_common.h>
 #include <acpi/acpi.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/apob_cache.h>
@@ -10,13 +11,9 @@
 #include <fsp/api.h>
 #include <program_loading.h>

-asmlinkage void car_stage_entry(void)
+void romstage_main(void)
 {
    post_code(0x40);
-	console_init();
-
-	post_code(0x41);
-
    /* Snapshot chipset state prior to any FSP call */
    fill_chipset_state();

diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 7e20768..b820497 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -10,14 +10,11 @@
 #include <fsp/api.h>
 #include <program_loading.h>
 #include <types.h>
+#include <romstage_common.h>

-asmlinkage void car_stage_entry(void)
+void romstage_main(void)
 {
    post_code(0x40);
-	console_init();
-
-	post_code(0x42);
-
    /* Snapshot chipset state prior to any FSP call. */
    fill_chipset_state();

diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index e316d21..59b7d51 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -23,6 +23,7 @@
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <amdblocks/psp.h>
+#include <romstage_common.h>

#include "chip.h"

@@ -47,7 +48,7 @@
    agesa_call();
 }

-asmlinkage void car_stage_entry(void)
+void romstage_main(void)
 {
    struct postcar_frame pcf;
    uintptr_t top_of_ram;
@@ -57,8 +58,6 @@
    int s3_resume = acpi_is_wakeup_s3();
    int i;

-	console_init();
-
    soc_enable_psp_early();
    if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
    	psp_load_named_blob(BLOB_SMU_FW, "smu_fw");
diff --git a/src/soc/example/min86/romstage.c b/src/soc/example/min86/romstage.c
index 91074b2..2b207f8 100644
--- a/src/soc/example/min86/romstage.c
+++ b/src/soc/example/min86/romstage.c
@@ -1,7 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <romstage_common.h>
 #include <arch/cpu.h>

-asmlinkage void car_stage_entry(void)
+void romstage_main(void)
 {
 }