Change in coreboot[master]: soc/mediatek/mt8192: Get DDR base information after calibration
Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44712
to review the following change.
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/1
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index adabb80..31e8d0e 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3835,6 +3835,36 @@ write32(regs_bak[i].addr, regs_bak[i].value); }
+u8 dramc_mode_reg_read(u8 chn, u8 mr_idx) +{ + u8 value; + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1); + + /* Wait until MRW command fired */ + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE) == 0) + udelay(1); + + value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0); + dramc_dbg("Read MR%d =%#x\n", mr_idx, value); + + return value; +} + +u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value = 0; + u8 rank_bak; + + rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak); + return value; +} + void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, u8 chn, u8 rank, u8 mr_idx, u8 value) { diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 355cc9d..cf199dc 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -14,6 +14,55 @@ mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); }
+static void get_dram_info_after_cal(struct ddr_cali *cali) +{ + u8 vendor_id, density, max_density = 0; + u32 size_Gb, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff; + dramc_info("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff; + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + size_Gb = 4; + break; + case 0x1: + size_Gb = 6; + break; + case 0x2: + size_Gb = 8; + break; + case 0x3: + size_Gb = 12; + break; + case 0x4: + size_Gb = 16; + break; + case 0x5: + size_Gb = 24; + break; + case 0x6: + size_Gb = 32; + break; + default: + size_Gb = 0; + break; + } + if (size_Gb > max_size) { + max_size = size_Gb; + max_density = density; + } + dramc_dbg("RK%d size %dGb, density:%d\n", rk, size_Gb, max_density); + } + + cali->density = max_density; +} + static void dramc_calibration_all_channels(struct ddr_cali *cali) { } @@ -91,6 +140,10 @@
dramc_calibration_all_channels(&cali);
+ /* only need do once for get DDR's base information */ + if (first_freq_k) + get_dram_info_after_cal(&cali); + first_freq_k= false; } }
Hello build bot (Jenkins), Julius Werner, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44712
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/2
Yidi Lin has uploaded a new patch set (#24) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/24
Yidi Lin has uploaded a new patch set (#34) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/34
Yidi Lin has uploaded a new patch set (#36) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/36
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
Patch Set 41:
(8 comments)
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 3844: while Can we use wait_us?
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 3849: = One space after "="
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 3856: = 0 No need for initialization.
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 17: static void get_dram_info_after_cal(struct ddr_cali *cali) If cali->density is the only thing modified in this function, why not return max_density?
static u8 get_dram_density(const struct ddr_cali *cali);
or
static u8 get_dram_density(u32 support_ranks);
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 20: G g
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 52: default If this indicates an error, please print an error message.
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 60: d u
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 134: only need do once for Only need to do once to
Yidi Lin has uploaded a new patch set (#44) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/44
Xi Chen has uploaded a new patch set (#45) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 91 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/45
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
Patch Set 45:
(8 comments)
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 3844: while
Can we use wait_us?
i use wait_ms, timeout: 10 seconds.
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 3849: =
One space after "="
Ack
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 3856: = 0
No need for initialization.
Ack
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 17: static void get_dram_info_after_cal(struct ddr_cali *cali)
If cali->density is the only thing modified in this function, why not return max_density? […]
Actually, get dram info contains vendor id, density and so on. As you noticed, here, we only save the density for use, maybe other information will be saved for future use. so we want to keep "get_dram_info*" function name, is it ok?
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 20: G
g
Ack
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 52: default
If this indicates an error, please print an error message.
Ack
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 60: d
u
Ack
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 134: only need do once for
Only need to do once to
Ack
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
Patch Set 45:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44712/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/45/src/soc/mediatek/mt8192/dr... PS45, Line 3845: if (!wait_ms(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE))) { line over 96 characters
Xi Chen has uploaded a new patch set (#46) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 92 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/46
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
Patch Set 46:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44712/46//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44712/46//COMMIT_MSG@8 PS46, Line 8: Please paste the new log messages.
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... PS46, Line 3867: return value; Please add a blank line above.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
Patch Set 46:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 3844: while
i use wait_ms, timeout: 10 seconds.
Ack
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... PS46, Line 3846: SPCMDRESP_MRR_RESPONSE Align with &ch[chn]
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 17: static void get_dram_info_after_cal(struct ddr_cali *cali)
Actually, get dram info contains vendor id, density and so on. […]
Ack
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... PS46, Line 57: 0x%#x %#x
Xi Chen has uploaded a new patch set (#47) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
After calibration, we can get ddr vendor id or density info from MR5 or MR8, this helps to make sure the DDR HW is as we expected.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 93 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/47
Attention is currently required from: Paul Menzel, CK HU, Yu-Ping Wu. Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
Patch Set 47:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/44712/comment/213b877a_878834ef PS46, Line 8:
Please paste the new log messages.
Done
File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/comment/6fd1be26_d8c75a99 PS46, Line 3846: SPCMDRESP_MRR_RESPONSE
Align with &ch[chn]
Ack
https://review.coreboot.org/c/coreboot/+/44712/comment/fe11e1b1_211676e1 PS46, Line 3867: return value;
Please add a blank line above.
Ack
File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44712/comment/a246caa7_47477623 PS46, Line 57: 0x%#x
%#x
Ack
Attention is currently required from: Xi Chen, Paul Menzel, CK HU. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
Patch Set 47: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
soc/mediatek/mt8192: Get DDR base information after calibration
After calibration, we can get ddr vendor id or density info from MR5 or MR8, this helps to make sure the DDR HW is as we expected.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44712 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 93 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index e2ca919..7f8d83a 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3833,6 +3833,41 @@ write32(regs_bak[i].addr, regs_bak[i].value); }
+u8 dramc_mode_reg_read(u8 chn, u8 mr_idx) +{ + const u32 timeout = 10000; + u8 value; + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1); + + /* Wait until MRW command fired */ + if (!wait_ms(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp, + SPCMDRESP_MRR_RESPONSE))) { + dramc_err("Read mode register time out\n"); + return -1; + } + + value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0); + dramc_dbg("Read MR%d = %#x\n", mr_idx, value); + + return value; +} + +u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value; + u8 rank_bak; + + rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak); + + return value; +} + void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, u8 chn, u8 rank, u8 mr_idx, u8 value) { diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index fb86305..8eba016 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -14,6 +14,60 @@ mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore); }
+static void get_dram_info_after_cal(struct ddr_cali *cali) +{ + u8 vendor_id, density, max_density = 0; + u32 size_gb, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff; + dramc_info("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff; + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + /* these case values are from JESD209-4C MR8 Density OP[5:2] */ + case 0x0: + size_gb = 4; + break; + case 0x1: + size_gb = 6; + break; + case 0x2: + size_gb = 8; + break; + case 0x3: + size_gb = 12; + break; + case 0x4: + size_gb = 16; + break; + case 0x5: + size_gb = 24; + break; + case 0x6: + size_gb = 32; + break; + case 0xC: + size_gb = 2; + break; + default: + dramc_err("Unexpected mode register density value: %#x\n", density); + size_gb = 0; + break; + } + if (size_gb > max_size) { + max_size = size_gb; + max_density = density; + } + dramc_dbg("RK%u size %uGb, density:%u\n", rk, size_gb, max_density); + } + + cali->density = max_density; +} + static void dramc_calibration_all_channels(struct ddr_cali *cali) { } @@ -82,6 +136,10 @@
dramc_calibration_all_channels(&cali);
+ /* only need to do once to get DDR's base information */ + if (first_freq_k) + get_dram_info_after_cal(&cali); + first_freq_k = false; } }
-
build bot (Jenkins) (Code Review) -
CK HU (Code Review)
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Hung-Te Lin (Code Review)
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Paul Menzel (Code Review)
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Xi Chen (Code Review)
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Yidi Lin (Code Review)
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Yu-Ping Wu (Code Review)