Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuaration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h 3 files changed, 473 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/1
diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 80a3edf..0472346 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -6,18 +6,393 @@ * SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h> +#include <arch/acpi.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <baseboard/gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h>
-/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { + /* A0 thru A6 are ESPI, configured elsewhere */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : GPP_A7 ==> CNVI_EN# */ + PAD_CFG_GPI(GPP_A7, NONE, PLTRST), + /* A8 : GPP_A8 ==> CNV_RF_RESET# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + /* A9 : GPP_A9 ==> CLKREQ_CNV#_1P8 */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + /* A10 : GPP_A10 ==> TOUCH_SCREEN_RST# */ + PAD_CFG_GPO(GPP_A10, 0, PLTRST), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : GPP_A12 ==> M2280_PCIE_SATA# */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : GPP_A13 ==> PCH_BT_RADIO_DIS# */ + PAD_CFG_GPO(GPP_A13, 0, PLTRST), + /* A14 : GPP_A14 ==> USB_OC1# */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : GPP_A15 ==> USB_OC2# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : GPP_A16 ==> USB_OC3# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : GPP_A17 ==> NC */ + PAD_NC(GPP_A17, NONE), + /* A18 : GPP_A18 ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : GPP_A19 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : GPP_A20 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : GPP_A21 ==> 3.3V_CAM_EN# */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), + /* A22 : GPP_A22 ==> KB_DET# */ + PAD_CFG_GPI(GPP_A22, NONE, PLTRST), + /* A23 : GPP_A23 ==> RECOVERY# */ + PAD_CFG_GPI(GPP_A23, NONE, DEEP),
-}; + /* B0 : GPP_B0 ==> CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : GPP_B1 ==> CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : GPP_B2 ==> VRALERT_L */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : GPP_B3 ==> TOUCH_SCREEN_PD# */ + PAD_CFG_GPO(GPP_B3, 0, PLTRST), + /* B4 : GPP_B4 ==> TOUCH_SCREEN_DET# */ + PAD_CFG_GPI(GPP_B4, NONE, PLTRST), + /* B5 : GPP_B5 ==> ISH_I2C0_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : GPP_B6 ==> ISH_I2C0_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : GPP_B7 ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : GPP_B8 ==> NC */ + PAD_NC(GPP_B8, NONE), + /* B9 : GPP_B9 ==> NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : GPP_B10 ===> NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : GPP_B11 ==> TBT_I2C_INT# */ + PAD_CFG_GPI_APIC(GPP_B11, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* B12 : GPP_B12 ==> SIO_SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PCH_PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : GPP_B14 ==> SPKR (PIN STRAP, Top Swap Override) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* B15 : GPP_B15 ==> SPK_DET0# */ + PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + /* B16 : GPP_B16 ==> ONE_DIMM# */ + PAD_CFG_GPI(GPP_B16, NONE, PLTRST), + /* B17 : GPP_B17 ==> HOST_SD_WP# */ + PAD_CFG_GPO(GPP_B17, 0, PLTRST), + /* B18 : GPP_B18 ==> NRB_BIT (PIN STRAP, No Reboot */ + PAD_NC(GPP_B18, NONE), + /* B19 : GPP_B19 ==> D3_RST# */ + PAD_CFG_GPO(GPP_B19, 0, PLTRST), + /* B20 : GPP_B20 ==> LCD_CBL_DET# */ + PAD_CFG_GPI(GPP_B20, NONE, PLTRST), + /* B21 : GPP_B21 ==> PCH_TOUCH_SCREEN_EN */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + /* B22 : GPP_B22 ==> NC */ + PAD_NC(GPP_B22, NONE), + /* B23 : GPP_B23 ==> NC (PIN STRAP, CPUNSSC frequency) */ + PAD_NC(GPP_B23, DN_20K),
-/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { + /* C0 : GPP_C0 ==> MEM_SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : GPP_C1 ==> MEM_SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2 : GPP_C2 ==> NC (PIN STRAP, TLS Confidentiality) */ + PAD_NC(GPP_C2, NONE), + /* C3 : GPP_C3 ==> SML0_SMBCLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : GPP_C4 ==> SML0_SMBDATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : GPP_C5 ==> NC (PIN STRAP, Boot Strap 0) */ + PAD_NC(GPP_C5, NONE), + /* C6 : GPP_C6 ==> SML1_SMBCLK */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7 : GPP_C7 ==> SML1_SMBDATA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* C8 : GPP_C8 ==> WWAN_FULL_POWER_EN */ + PAD_CFG_GPO(GPP_C8, 0, PLTRST), + /* C9 : GPP_C9 ==> SBIOS_TX */ + PAD_CFG_GPO(GPP_C9, 0, PLTRST), + /* C10 : GPP_C10 ==> NC */ + PAD_NC(GPP_C10, NONE), + /* C11 : GPP_C11 ==> NC */ + PAD_NC(GPP_C11, NONE), + /* C12 : GPP_C12 ==> NC */ + PAD_NC(GPP_C12, NONE), + /* C13 : GPP_C13 ==> PCH_SSD_PWR_EN */ + PAD_CFG_GPO(GPP_C13, 0, PLTRST), + /* C14 : GPP_C14 ==> NC */ + PAD_NC(GPP_C14, NONE), + /* C15 : GPP_C15 ==> NC */ + PAD_NC(GPP_C15, NONE), + /* C16 : GPP_C16 ==> I2C0_SDA_TS */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : GPP_C17 ==> I2C0_SCL_TS */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : GPP_C18 ==> I2C1_SDA_TP */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : GPP_C19 ==> I2C1_SCL_TP */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART - programmed in early table */ + /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART - programmed in early table */ + /* C22 : GPP_C22 ==> H1_FLASH_WP */ + PAD_CFG_GPI(GPP_C22, NONE, PLTRST), + /* C23 : GPP_C23 ==> H1_PCH_INT# */ + PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT),
+ /* D0 : GPP_D0 ==> ISH_ACC1_INT */ + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + /* D1 : GPP_D1 ==> ISH_ACC2_INT */ + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + /* D2 : GPP_D2 ==> ISH_TABLE_MODE# */ + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + /* D3 : GPP_D3 ==> ISH_ALS_INT# */ + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + /* D4 : GPP_D4 ==> RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D5 : GPP_D5 ==> CLKREQ_PCIE#0 */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : GPP_D6 ==> CLKREQ_PCIE#1 */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : GPP_D7 ==> CLKREQ_PCIE#2 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : GPP_D8 ==> CLKREQ_PCIE#3 */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : GPP_D9 ==> TBT_2_LSX_TX */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + /* D10 : GPP_D10 ==> TBT_2_LSX_RX */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + /* D11 : GPP_D11 ==> TBT_3_LSX_TX */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), + /* D12 : GPP_D12 ==> TBT_3_LSX_RX */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF4), + /* D13 : GPP_D13 ==> SML0B_SMLDATA */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + /* D14 : GPP_D14 ==> SML0B_SMLCLK */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), + /* D15 : GPP_D15 ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : GPP_D16 ==> SML0BALERT# */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + /* D17 : GPP_D17 ==> ISH_NB_MODE# */ + PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), + /* D18 : GPP_D18 ==> ISH_LID_CL#_NB */ + PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), + /* D19 : GPP_D19 ==> NC */ + PAD_NC(GPP_D19, NONE), + + /* E0 : GPP_E0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : GPP_E1 ==> TOUCH_SCREEN_INT# */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, PLTRST, EDGE_SINGLE), + /* E2 : GPP_E2 ==> MEDIACARD_IRQ# */ + PAD_CFG_GPI_APIC(GPP_E2, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ + PAD_CFG_GPI(GPP_E3, NONE, PLTRST), + /* E4 : GPP_E4 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : GPP_E5 ==> M2280_DEVSLP */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : GPP_E6 ==> (PIN STRAP, Reserved) */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> PCH_TOUCHPAD_INTR# */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* E8 : GPP_E8 ==> SECURE_BIO */ + PAD_CFG_GPO(GPP_E8, 0, PLTRST), + /* E9 : GPP_E9 ==> OC0# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : GPP_E10 ==> HDMI_PD# */ + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + /* E11 : GPP_E11 ==> VPRO_DET# */ + PAD_CFG_GPI(GPP_E11, NONE, PLTRST), + /* E12 : GPP_E12 ==> RTC_DET# */ + PAD_CFG_GPI(GPP_E12, NONE, PLTRST), + /* E13 : GPP_E13 ==> TBT_DET# */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E14 : GPP_E14 ==> EPD_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : GPP_E15 ==> ISH_LID_CL#_TAB */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + /* E16 : GPP_E16 ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : GPP_E17 ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : GPP_E18 ==> TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : GPP_E19 ==> TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : GPP_E20 ==> TBT_LSX1_TXD */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : GPP_E21 ==> TBT_LSX1_RXD */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : GPP_E22 ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : GPP_E23 ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F0 : GPP_F0 ==> BRI_DT_1P8 */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : GPP_F1 ==> CNV_BRI_RSP_1P8 */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : GPP_F2 ==> CNV_RGI_DT_1P8 */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : GPP_F3 ==> CNV_RGI_RSP_1P8 */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : GPP_F4 ==> NC */ + PAD_NC(GPP_F4, NONE), + /* F5 : GPP_F5 ==> NC */ + PAD_NC(GPP_F5, NONE), + /* F6 : GPP_F6 ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F7 : GPP_F7 ==> NC (PIN STRAP, Reserved) */ + PAD_NC(GPP_F7, DN_20K), + /* F8 : GPP_F8 ==> NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : GPP_F9 ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPP_F10 ==> NC (PIN STRAP, Reserved) */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 - programmed in early table */ + /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 - programmed in early table */ + /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 - programmed in early table */ + /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 - programmed in early table */ + /* F15 : GPP_F11 ==> MEM_CONFIG4_1P8 - programmed in early table */ + /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ + PAD_CFG_GPO(GPP_F16, 1, PLTRST), + /* F17 : GPP_F17 ==> WWAN_GPIO_PERST# */ + PAD_CFG_GPO(GPP_F17, 0, PLTRST), + /* F18 : GPP_F18 ==> WWAN_GPIO_WAKE# */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : GPP_F19 ==> CAM_MIC_CBL_DET# */ + PAD_CFG_GPI(GPP_F19, NONE, PLTRST), + /* F20 : GPP_F20 ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : GPP_F21 ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), + /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ + PAD_CFG_GPI(GPP_H4, NONE, DEEP), + /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ + PAD_CFG_GPI(GPP_H5, NONE, DEEP), + /* H6 : GPP_H6 ==> SPK_DET1 */ + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), + /* H7 : GPP_H7 ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* H12 : GPP_H12 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13 ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14 ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : GPP_H15 ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : GPP_H16 ==> CPU_DPB_CTRL_CLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : GPP_H17 ==> CPU_DPB_CTRL_DATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : GPP_H19 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : GPP_H20 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : GPP_H21 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : GPP_H22 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : GPP_H23 ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R0 : GPP_R0 ==> HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* R1 : GPP_R1 ==> HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), + /* R2 : GPP_R2 ==> HDA_SDO (PIN STRAP, Flash Descriptor Security Override */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF1), + /* R3 : GPP_R3 ==> HDA_SDIO */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), + /* R4 : GPP_R4 ==> HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* R5 : GPP_R5 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : GPP_R6 ==> SD_PWR_EN1 */ + PAD_CFG_GPO(GPP_R6, 0, PLTRST), + /* R7 : GPP_R7 ==> SD_PWR_EN2 */ + PAD_CFG_GPO(GPP_R7, 0, PLTRST), + + /* S0 : GPP_S0 ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : GPP_S1 ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : GPP_S2 ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : GPP_S3 ==> NC */ + PAD_NC(GPP_S3, NONE), + /* S4 : GPP_S4 ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : GPP_S5 ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : GPP_S6 ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : GPP_S7 ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD0: GPD0 ==> PCH_BATLOW# */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: GPD1 ==> AC_PRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: GPD2 ==> LAN_WAKE# */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: GPD3 ==> SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: GPD4 ==> SIO_SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: GPD5 ==> SIO_SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: GPD6 ==> SIO_SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7 ==> PCH_TBT_PERST# (PIN STRAP, Reserved) */ + PAD_CFG_GPO(GPD7, 0, PLTRST), + /* GPD8: GPD8 ==> SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: GPD9 ==> SIO_SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: GPD10 ==> SIO_SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: GPD11 ==> PM_LANPHY_EN */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), };
const struct pad_config *__weak variant_base_gpio_table(size_t *num) @@ -26,24 +401,79 @@ return gpio_table; }
+/* GPIO pads configured in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A23 : GPP_A23 ==> RECOVERY# */ + PAD_CFG_GPI(GPP_A23, NONE, DEEP), + /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : GPP_C22 ==> H1_FLASH_WP */ + PAD_CFG_GPI(GPP_C22, NONE, PLTRST), + /* C23 : GPP_C23 ==> H1_PCH_INT# */ + PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ + PAD_CFG_GPI(GPP_E3, NONE, PLTRST), + /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */ + PAD_CFG_GPI(GPP_F11, NONE, DEEP), + /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */ + PAD_CFG_GPI(GPP_F13, NONE, DEEP), + /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */ + PAD_CFG_GPI(GPP_F14, NONE, DEEP), + /* F15 : GPP_F11 ==> MEM_CONFIG4_1P8 */ + PAD_CFG_GPI(GPP_F15, NONE, DEEP), + /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ + PAD_CFG_GPO(GPP_F16, 0, PLTRST), + /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ + PAD_CFG_GPI(GPP_H4, NONE, DEEP), + /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ + PAD_CFG_GPI(GPP_H5, NONE, DEEP), + /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* GPD3: GPD3 ==> SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +}; + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_NAME), +}; + +const struct cros_gpio *__weak override_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} + +/* Weak implementation of overrides */ const struct pad_config *__weak variant_override_gpio_table(size_t *num) { *num = 0; return NULL; }
-const struct pad_config *__weak variant_early_gpio_table(size_t *num) +/* Weak implementation of early gpio */ +const struct pad_config *__weak override_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; }
-static const struct cros_gpio cros_gpios[] = { - -}; - -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +void variant_mainboard_post_init_params(FSPM_UPD *mupd) { - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; + /* + * Disable memory channel by HW strap pin, HW default is enable + * 0: Enable both DIMMs, 3: Disable both DIMMs + */ + /* + * TODO: I don't see the correct UPDs available in the partial headers + * + * mupd->FspmConfig.DisableDimmChannel0 = gpio_get(DDR_CHA_EN) ? 0 : 3; + * mupd->FspmConfig.DisableDimmChannel1 = gpio_get(DDR_CHB_EN) ? 0 : 3; + */ } diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index e1db2aa..bd47841 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -6,10 +6,33 @@ * SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H
+#include <soc/gpe.h> #include <soc/gpio.h>
+/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_C22
-#endif /* BASEBOARD_GPIO_H */ +/* Recovery mode */ +#define GPIO_REC_MODE GPP_A23 + +/* DDR channel enable pin */ +#define DDR_CHA_EN GPP_H4 +#define DDR_CHB_EN GPP_H5 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F11 +#define GPIO_MEM_CONFIG_1 GPP_F12 +#define GPIO_MEM_CONFIG_2 GPP_F13 +#define GPIO_MEM_CONFIG_3 GPP_F14 +#define GPIO_MEM_CONFIG_4 GPP_F15 + + +const struct pad_config *override_gpio_table(size_t *num); +const struct pad_config *override_early_gpio_table(size_t *num); +struct cros_gpio; +const struct cros_gpio *override_cros_gpios(size_t *num); + +#endif diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index bffaa22..d0cdf778 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -9,6 +9,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__
+#include <fsp/api.h> #include <soc/gpio.h> #include <stddef.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -20,7 +21,8 @@ const struct pad_config *variant_base_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); - const struct cros_gpio *variant_cros_gpios(size_t *num);
+void variant_mainboard_post_init_params(FSPM_UPD *mupd); + #endif /* __BASEBOARD_VARIANTS_H__ */
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Bernardo Perez Priego, Karthik Ramasubramanian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#2).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h 3 files changed, 473 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 439: PAD_CFG_NF(GPD3, NONE, DEEP, NF1), Please UP20K. https://review.coreboot.org/c/coreboot/+/30374
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 474: * TODO: I don't see the correct UPDs available in the partial headers I will check this.
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 474: * TODO: I don't see the correct UPDs available in the partial headers
I will check this.
This is in FSP but not export to vendor code, I will ask Intel export it, Eric.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 474: * TODO: I don't see the correct UPDs available in the partial headers
This is in FSP but not export to vendor code, I will ask Intel export it, Eric.
It is already being handled by meminit_tgl.c: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/m...
The field is currently just marked as reserved.
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 2:
(1 comment)
Patch Set 2:
(1 comment)
@Furquan, this is use for disable channel not dimm1 only. I would like to talk with Sabrata for export this 😊
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 474: * TODO: I don't see the correct UPDs available in the partial headers
It is already being handled by meminit_tgl.c: https://review.coreboot.org/cgit/coreboot. […]
This feature is for disable channel.. It seems like we can't do this if TGL meminit always config by hardcode....Eric.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 2:
(1 comment)
Patch Set 2:
(1 comment)
Patch Set 2:
(1 comment)
@Furquan, this is use for disable channel not dimm1 only. I would like to talk with Sabrata for export this 😊
For
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 474: * TODO: I don't see the correct UPDs available in the partial headers
This feature is for disable channel.. […]
Disabling of channel can be done by passing in half-populated flag into meminit_lpddr4x_dimm0(): https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/i...
Based on that half_populated flag (which means only 1 channel is used), SoC code sets up SPD and channel disabling accordingly here: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/m...
P.S.: As per TGL EDS, it is possible to only disable logical channel1 and not logical channel0.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 2:
Patch Set 2:
(1 comment)
Patch Set 2:
(1 comment)
Patch Set 2:
(1 comment)
@Furquan, this is use for disable channel not dimm1 only. I would like to talk with Sabrata for export this 😊
For
Okay, I think I can talk with Intel. Because this feature is worked on CML. I think it can support it due to Windows can support this as well.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 439: PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
Please UP20K. https://review.coreboot. […]
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 474: * TODO: I don't see the correct UPDs available in the partial headers
Disabling of channel can be done by passing in half-populated flag into meminit_lpddr4x_dimm0(): htt […]
Intel will add it back to FSPM header. We can enable this after that.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/3/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/3/src/mainboard/google/deltau... PS3, Line 273: PAD_CFG_GPO(GPP_F16, 1, PLTRST), Please set this low in early table 😊 Should be the last change needed. Thanks for your hard working.
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#4).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h 3 files changed, 473 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/4
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 4: Code-Review+2
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#5).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h 3 files changed, 472 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/5
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/2/src/mainboard/google/deltau... PS2, Line 474: * TODO: I don't see the correct UPDs available in the partial headers
Intel will add it back to FSPM header. We can enable this after that.
Ack
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/3/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/3/src/mainboard/google/deltau... PS3, Line 273: PAD_CFG_GPO(GPP_F16, 1, PLTRST),
Please set this low in early table 😊 […]
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 6: Code-Review+2
whoops, looks like I still missing one but you correct it 😄
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 57: PAD_CFG_GPI This GPIO is configured in early table - same config. So do we need to configure it again?
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 151: PAD_CFG_GPI(GPP_C22, NONE, PLTRST), : /* C23 : GPP_C23 ==> H1_PCH_INT# */ : PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT), Configured in early table.
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 203: PAD_CFG_GPI(GPP_E3, NONE, PLTRST), Configured in Early table.
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 271: GPP_F11 Nit: GPP_F15
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 425: GPP_F11 Nit: GPP_F15
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 6:
Since these changes are based on Deltan schematics, shouldn't they be under variants/deltan/gpio.c rather than baseboard? Deltaur is baseboard, deltan is variant.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 6:
Patch Set 6:
Since these changes are based on Deltan schematics, shouldn't they be under variants/deltan/gpio.c rather than baseboard? Deltaur is baseboard, deltan is variant.
Most of them should end up being common, so they can use the base table for the bulk of the configuration. Once the Deltaur schematics are done (last I checked, they definitely were not), I was going to go through them and split out the differences into the two variants.
Does that sound like an okay plan?
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, Karthik Ramasubramanian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#7).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h 3 files changed, 469 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/7
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 7:
Patch Set 6:
Patch Set 6:
Since these changes are based on Deltan schematics, shouldn't they be under variants/deltan/gpio.c rather than baseboard? Deltaur is baseboard, deltan is variant.
Most of them should end up being common, so they can use the base table for the bulk of the configuration. Once the Deltaur schematics are done (last I checked, they definitely were not), I was going to go through them and split out the differences into the two variants.
Does that sound like an okay plan?
Okay, understood.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 7:
(12 comments)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 25: PLTRST What is the reason behind configuring this as PLTRST?
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 31: PLTRST Same here and the rest of entries below. I am mostly referring to GPIOs that are acting as output from the SoC and are reset/enable lines. Is the intent that those should return to their default state on PLTRST so that it can power cycle or reset external devices? Do all these lines have external pulls to guarantee this happens?
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 56: programmed in early table We should still configure all pads in ramstage. This is also helpful in case any gpio has to be overriden by variant.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 81: EDGE_SINGLE We have been using LEVEL at the pad so that the signal just goes unmodified to the APIC and the trigger is applied at the APIC.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 134: 0 SSD power being set to 0? Do you intend to change this later?
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 147: early table Please see my comment above about configuring all GPIOs in this table.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 196: PAD_CFG_GPI_SCI_LOW Why SCI? Touchscreen is not a wake source. This can simply be PAD_CFG_GPI_APIC.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 198: EDGE_SINGLE LEVEL
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 208: EDGE_SINGLE LEVEL
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 340: DN_20K Why does this have an internal PD?
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 411: EDGE_SINGLE LEVEL
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 26: void variant_mainboard_post_init_params(FSPM_UPD *mupd); Not related to this change?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 57: PAD_CFG_GPI
This GPIO is configured in early table - same config. […]
Done
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 151: PAD_CFG_GPI(GPP_C22, NONE, PLTRST), : /* C23 : GPP_C23 ==> H1_PCH_INT# */ : PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT),
Configured in early table.
Done
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 203: PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
Configured in Early table.
Done
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 271: GPP_F11
Nit: GPP_F15
Done
https://review.coreboot.org/c/coreboot/+/39674/6/src/mainboard/google/deltau... PS6, Line 425: GPP_F11
Nit: GPP_F15
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 7:
(11 comments)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 25: PLTRST
What is the reason behind configuring this as PLTRST?
The EEs provided us a GPIO table with the listed reset source for each. Although the schematic and the GPIO table disagree about whether this is an input or output. From the schematic, this looks like an output to EC, presumably so it can power sequence the CNVi?
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 31: PLTRST
Same here and the rest of entries below. […]
PLTRST also controls power to at least the touch screen, SSD, and WLAN. No point in saving the state beyond PLTRST any way then.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 56: programmed in early table
We should still configure all pads in ramstage. […]
Done
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 81: EDGE_SINGLE
We have been using LEVEL at the pad so that the signal just goes unmodified to the APIC and the trig […]
Done
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 134: 0
SSD power being set to 0? Do you intend to change this later?
I think I must have misread a # at the end 😊
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 147: early table
Please see my comment above about configuring all GPIOs in this table.
Done
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 196: PAD_CFG_GPI_SCI_LOW
Why SCI? Touchscreen is not a wake source. This can simply be PAD_CFG_GPI_APIC.
Done
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 198: EDGE_SINGLE
LEVEL
Done
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 208: EDGE_SINGLE
LEVEL
Also I think this is the one that should be PAD_CFG_GPI_IRQ_WAKE
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 340: DN_20K
Why does this have an internal PD?
The schematic has it labeled that way, "WEAK INTERNAL PD 20K". All of the Strapping Pins are labeled so as to use the internal pulls. I'm not sure why, as I don't think the strapping pins matter (for strapping purposes) by the time we get to ramstage 😊 (coincidence?)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 411: EDGE_SINGLE
LEVEL
Whoops
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, Karthik Ramasubramanian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#8).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h 3 files changed, 479 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 8:
(17 comments)
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 57: PAD_CFG_GPI(GPP_A23, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 57: PAD_CFG_GPI(GPP_A23, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 149: PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 149: PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 151: PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 151: PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 152: /* C22 : GPP_C22 ==> H1_FLASH_WP */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 270: PAD_CFG_GPI(GPP_F11, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 270: PAD_CFG_GPI(GPP_F11, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 272: PAD_CFG_GPI(GPP_F12, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 272: PAD_CFG_GPI(GPP_F12, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 274: PAD_CFG_GPI(GPP_F13, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 274: PAD_CFG_GPI(GPP_F13, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 276: PAD_CFG_GPI(GPP_F14, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 276: PAD_CFG_GPI(GPP_F14, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 278: PAD_CFG_GPI(GPP_F15, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/8/src/mainboard/google/deltau... PS8, Line 278: PAD_CFG_GPI(GPP_F15, NONE, DEEP), please, no spaces at the start of a line
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, Karthik Ramasubramanian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#9).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h 3 files changed, 480 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 9:
(19 comments)
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 57: PAD_CFG_GPI(GPP_A23, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 57: PAD_CFG_GPI(GPP_A23, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 149: PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 149: PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 151: PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 151: PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 152: /* C22 : GPP_C22 ==> H1_FLASH_WP */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 270: PAD_CFG_GPI(GPP_F11, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 270: PAD_CFG_GPI(GPP_F11, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 272: PAD_CFG_GPI(GPP_F12, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 272: PAD_CFG_GPI(GPP_F12, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 274: PAD_CFG_GPI(GPP_F13, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 274: PAD_CFG_GPI(GPP_F13, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 276: PAD_CFG_GPI(GPP_F14, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 276: PAD_CFG_GPI(GPP_F14, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 278: PAD_CFG_GPI(GPP_F15, NONE, DEEP), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 278: PAD_CFG_GPI(GPP_F15, NONE, DEEP), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 386: PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39674/9/src/mainboard/google/deltau... PS9, Line 386: PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), please, no spaces at the start of a line
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, Karthik Ramasubramanian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#10).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h 3 files changed, 480 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/10
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 10:
(13 comments)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 25: PLTRST
The EEs provided us a GPIO table with the listed reset source for each. […]
Interesting. Humm.. It would be good to understand how this pin actually gets used.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 31: PLTRST
PLTRST also controls power to at least the touch screen, SSD, and WLAN. […]
That sounds mostly fine.
Thinking out loud: Difference in reset config between DEEP and PLTRST is S3/S4/S5 i.e. DEEP retains state across trip to S3/S4/S5. On the other hand, PLTRST results in GPIO pad config resetting to default on entry into S3/S4/S5.
When you say power to these devices(WLAN,SSD,touchscreen) is controlled by PLTRST#, does it mean that PLTRST# is like a master switch for enabling the VRs for them? If yes, then this should work okay. It would be good to ensure that we still do not violate any power sequencing.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 208: EDGE_SINGLE
Also I think this is the one that should be PAD_CFG_GPI_IRQ_WAKE
Correct.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 340: DN_20K
The schematic has it labeled that way, "WEAK INTERNAL PD 20K". […]
So, the strapping pins actually could have some internal pull auto configured when they get sampled. This is to guarantee some default state of the straps in case there are no external pulls. However, that should be independent of what coreboot is configuring.
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 65: TOUCH_SCREEN_PD Does PD mean power down?
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 97: D3_RST I am not sure what the usage is. Is PLTRST the right setting for this?
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 106: DN_20K I don't think we need an internal pull here?
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 125: 0 Assuming you plan to do this as a follow-up?
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 126: SBIOS_TX What is this used for?
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 201: EDGE_SINGLE LEVEL?
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 250: UP_20K Required?
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 254: UP_20K Same here.
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 262: DN_20K I don't think this is needed. Same for other straps.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 147: early table
Done
Can we get the rom stage log if we put this in ramstage? Or UART pin default is NF1?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 97: D3_RST
I am not sure what the usage is. […]
This could be D3 cold power sequence pin. We not implement yet.. We tried before but SD card driver not ready for this.
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 125: 0
Assuming you plan to do this as a follow-up?
C8 should be high here for the power sequence.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 56: programmed in early table
Done
Maybe we can leave as comment? That should be clear enough. Because if we put the same pin in two place, sometimes it would go wrong by overwrite again... you have to maintain two place.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 10:
All output pin should config as DEEP for power saving. I just checked Sarien and Drallion. And all the enable pin should enable as default for the eDiag using.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 483: * mupd->FspmConfig.DisableDimmChannel0 = gpio_get(DDR_CHA_EN) ? 0 : 3; Header get update in https://review.coreboot.org/c/coreboot/+/39797. Next step is remove the hard code in meminit.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 10:
(12 comments)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 340: DN_20K
So, the strapping pins actually could have some internal pull auto configured when they get sampled. […]
Maybe that's what they're referring to on the schematic... sounds reasonable.
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 65: TOUCH_SCREEN_PD
Does PD mean power down?
I believe so; once it's inverted, the signal changes name to "DISP_ON" and goes to the display connector (I still haven't seen the schematic for the I/O board yet...)
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 97: D3_RST
This could be D3 cold power sequence pin. We not implement yet.. […]
I think Eric is right, it's connected to the reset signals for the SSD and card reader, so if it needs to keep state in D3 cold then DEEP is appropriate.
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 106: DN_20K
I don't think we need an internal pull here?
I'm starting to think the notes about the internal PD/PU on the strap pins were unrelated to the pull to be programmed. Removing.
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 125: 0
C8 should be high here for the power sequence.
Done
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 126: SBIOS_TX
What is this used for?
I don't know; it goes to the OEM's JTAG connector; it has a weak pull up to 3.3V. I'm guessing it is their BIOS UART output?
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 201: EDGE_SINGLE
LEVEL?
Done
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 250: UP_20K
Required?
Done
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 254: UP_20K
Same here.
Done
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 262: DN_20K
I don't think this is needed. Same for other straps.
Done
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 483: * mupd->FspmConfig.DisableDimmChannel0 = gpio_get(DDR_CHA_EN) ? 0 : 3;
Header get update in https://review.coreboot.org/c/coreboot/+/39797. […]
Ack. I will update this patch and we can add the memory init in another one. I think Intel was working on the patches needed for DRAM.
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 26: void variant_mainboard_post_init_params(FSPM_UPD *mupd);
Not related to this change?
Done
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#11).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 2 files changed, 466 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/11
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11: Code-Review+1
(6 comments)
Overall looks okay to me. Just added some comments about reset configuration v/s state in S3.
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 126: SBIOS_TX
I don't know; it goes to the OEM's JTAG connector; it has a weak pull up to 3.3V. […]
Oh okay. Might have to revisit this later based on the usage.
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 25: PLTRST Thinking about this again. I don't think you want to disable CNVi power in S3. It can be a wake source.
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 95: nit: missing )
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 135: PLTRST This will cause SSD power to be lost in S3 as well. I don't think that is the intent?
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 192: PLTRST Isn't ISH active in S3? Wouldn't you want these configurations to hold true in that case as well?
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 201: NONE INVERT
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11:
Patch Set 11: Code-Review+1
(6 comments)
Overall looks okay to me. Just added some comments about reset configuration v/s state in S3.
I will check device power enable pin again. For the Wilco eDiag request, we need enable device in coreboot for them to detect. Keep pin in deep is for S5 energy star certified. I don't think we consider S3 before... We always in the PASS margin..
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/10/src/mainboard/google/delta... PS10, Line 65: TOUCH_SCREEN_PD
I believe so; once it's inverted, the signal changes name to "DISP_ON" and goes to the display conne […]
This is actual enable pin in device tree. Touch power pin is B21... You can refer drallion. I just correct once... This very confusing due to the naming is from Windows schematic.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11:
(9 comments)
Check with HW for D4,E8,R6,R7. Others please change to Drallion's configuration 😊
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 25: PLTRST
Thinking about this again. I don't think you want to disable CNVi power in S3. […]
Drallion's configuration PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 37: PAD_CFG_GPO(GPP_A13, 0, PLTRST), Drallion's configuration PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 53: PAD_CFG_GPO(GPP_A21, 1, PLTRST), Drallion's configuration PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 102: PAD_CFG_GPO(GPP_B21, 0, PLTRST), Drallion's configuration PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 125: PAD_CFG_GPO(GPP_C8, 1, PLTRST), Drallion's configuration PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_FULL_PWR_EN */
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 135: PLTRST
This will cause SSD power to be lost in S3 as well. […]
This may used for SSD D3 cold power sequence.. We can change it later on. Can't find this in Drallion.
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 192: PLTRST
Isn't ISH active in S3? Wouldn't you want these configurations to hold true in that case as well?
Yes, need change to DEEP. Drallion's configuration PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 201: NONE
INVERT
Drallion's configuration PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, LEVEL, NONE), /* TS_INT# */ Invert not needed?
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 219: PAD_CFG_GPO(GPP_E10, 1, PLTRST), Drallion's configuration PAD_CFG_GPO(GPP_E16, 1, DEEP), /* HDMI_PD# */
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11:
(10 comments)
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 25: PLTRST
Drallion's configuration PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */
Done
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 37: PAD_CFG_GPO(GPP_A13, 0, PLTRST),
Drallion's configuration PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
Done
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 53: PAD_CFG_GPO(GPP_A21, 1, PLTRST),
Drallion's configuration PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3. […]
Done
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 95:
nit: missing )
Done
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 102: PAD_CFG_GPO(GPP_B21, 0, PLTRST),
Drallion's configuration PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3. […]
Done
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 125: PAD_CFG_GPO(GPP_C8, 1, PLTRST),
Drallion's configuration PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_FULL_PWR_EN */
Done
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 135: PLTRST
This may used for SSD D3 cold power sequence.. We can change it later on. […]
I'm starting to think the GPIO table is just wrong with all these resets... I'll go back over them all with a fine toothed comb.
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 192: PLTRST
Yes, need change to DEEP. […]
Done
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 201: NONE
Drallion's configuration PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, LEVEL, NONE), /* TS_INT# */ […]
It's definitely active-low, it's pulled up to 3.3V. Let's try invert for now.
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 219: PAD_CFG_GPO(GPP_E10, 1, PLTRST),
Drallion's configuration PAD_CFG_GPO(GPP_E16, 1, DEEP), /* HDMI_PD# */
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 25: PLTRST
Interesting. Humm.. It would be good to understand how this pin actually gets used.
Filed a bug, b/152393736
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 31: PLTRST
That sounds mostly fine. […]
Sorry meant to say the reset signal for these devices is PLTRST#. I will go through and double check the POR state for these signals.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 135: PLTRST
I'm starting to think the GPIO table is just wrong with all these resets... […]
If you means the table provide from HW, It's definitely wrong. So I always busy to fix the power leakage in S5...
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 201: NONE
It's definitely active-low, it's pulled up to 3.3V. Let's try invert for now.
Here is the Drallion and Sarien device tree for this pin. If we invert this, be sure change device tree as well. I think it's fine. ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/7/src/mainboard/google/deltau... PS7, Line 56: programmed in early table
Maybe we can leave as comment? That should be clear enough. […]
An X-Macro would be a decent way to only have to define in one place, but I don't think that would fly on coreboot 😊
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/11/src/mainboard/google/delta... PS11, Line 201: NONE
Here is the Drallion and Sarien device tree for this pin. […]
Ack
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Furquan Shaikh, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#12).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 2 files changed, 466 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/12
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Furquan Shaikh, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#13).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 2 files changed, 466 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/13
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Furquan Shaikh, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#15).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 3 files changed, 468 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/15
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 15: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE LEVEL
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
LEVEL
Sarien and Drallion both have it set as EDGE_SINGLE, so I didn't know if that is a wilco thing, and controlled by a a strapping option?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
Sarien and Drallion both have it set as EDGE_SINGLE, so I didn't know if that is a wilco thing, and […]
Actually it looks like there is no strapping option for this... Eric, do you know why sarien & drallion have this configured as EDGE_SINGLE ?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
Actually it looks like there is no strapping option for this... […]
I don't think it should be specific to wilco. H1 interrupt is edge-triggered independent of platform but the trigger gets applied at the APIC instead of the GPIO pad.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
I don't think it should be specific to wilco. […]
Ok, so the LEVEL here lets it go straight through to the APIC as-is. Why is it done that way for this IRQ in particular?
Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Furquan Shaikh, Selma Bensaid, Kevin Chowski, Bernardo Perez Priego, EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39674
to look at the new patch set (#16).
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 3 files changed, 468 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/16
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 16: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
Ok, so the LEVEL here lets it go straight through to the APIC as-is. […]
That is what we do for all APIC IRQs i.e. LEVEL at pad, trigger at APIC.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 16:
(1 comment)
Thanks for your help everyone!
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
That is what we do for all APIC IRQs i.e. LEVEL at pad, trigger at APIC.
Ack
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
Ack
We should ask Duncan for this history. And this could be Wilco things as well. We have many H1 particular setting for Wilco EC.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
We should ask Duncan for this history. And this could be Wilco things as well. […]
I'll make a note to ask him.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
I'll make a note to ask him.
You will get used to the weird demand from Wilco EC. The big challenge is H1 and Wilco is not compatible.
Varun Joshi has uploaded a new patch set (#18) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 3 files changed, 448 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/18
Varun Joshi has uploaded a new patch set (#19) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 3 files changed, 448 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/19
Varun Joshi has uploaded a new patch set (#20) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 3 files changed, 468 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39674/20
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39674/15/src/mainboard/google/delta... PS15, Line 153: EDGE_SINGLE
You will get used to the weird demand from Wilco EC. […]
Apologize, there was rebasing issue from my end after patch 16, Reverted back in patch 20.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
Patch Set 20: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39674 )
Change subject: mb/google/deltaur: Add initial GPIO configuration ......................................................................
mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of the board.
BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/39674 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h 3 files changed, 468 insertions(+), 22 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 1283788..5a0c481 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -6,6 +6,7 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <baseboard/gpio.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> @@ -17,7 +18,6 @@ #include <soc/pmc.h> #include <soc/pci_devs.h>
- enum rec_mode_state { REC_MODE_UNINITIALIZED, REC_MODE_NOT_REQUESTED, diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 3951ce0..a67dd8cb 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -4,18 +4,400 @@ * SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h> +#include <arch/acpi.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <baseboard/gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h>
-/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { + /* A0 thru A6 are ESPI, configured elsewhere */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : GPP_A7 ==> CNVI_EN# */ + PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : GPP_A8 ==> CNV_RF_RESET# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + /* A9 : GPP_A9 ==> CLKREQ_CNV#_1P8 */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + /* A10 : GPP_A10 ==> TOUCH_SCREEN_RST# */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : GPP_A12 ==> M2280_PCIE_SATA# */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : GPP_A13 ==> PCH_BT_RADIO_DIS# */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A14 : GPP_A14 ==> USB_OC1# */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : GPP_A15 ==> USB_OC2# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : GPP_A16 ==> USB_OC3# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : GPP_A17 ==> NC */ + PAD_NC(GPP_A17, NONE), + /* A18 : GPP_A18 ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : GPP_A19 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : GPP_A20 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : GPP_A21 ==> 3.3V_CAM_EN# */ + PAD_CFG_GPO(GPP_A21, 0, PLTRST), + /* A22 : GPP_A22 ==> KB_DET# */ + PAD_CFG_GPI(GPP_A22, NONE, PLTRST), + /* A23 : GPP_A23 ==> RECOVERY# */ + PAD_CFG_GPI(GPP_A23, NONE, DEEP),
-}; + /* B0 : GPP_B0 ==> CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : GPP_B1 ==> CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : GPP_B2 ==> VRALERT_L */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : GPP_B3 ==> TOUCH_SCREEN_PD# */ + PAD_CFG_GPO(GPP_B3, 0, PLTRST), + /* B4 : GPP_B4 ==> TOUCH_SCREEN_DET# */ + PAD_CFG_GPI(GPP_B4, NONE, DEEP), + /* B5 : GPP_B5 ==> ISH_I2C0_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : GPP_B6 ==> ISH_I2C0_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : GPP_B7 ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : GPP_B8 ==> NC */ + PAD_NC(GPP_B8, NONE), + /* B9 : GPP_B9 ==> NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : GPP_B10 ===> NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : GPP_B11 ==> TBT_I2C_INT# */ + PAD_CFG_GPI_APIC(GPP_B11, NONE, PLTRST, LEVEL, INVERT), + /* B12 : GPP_B12 ==> SIO_SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PCH_PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : GPP_B14 ==> SPKR (PIN STRAP, Top Swap Override) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* B15 : GPP_B15 ==> SPK_DET0# */ + PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + /* B16 : GPP_B16 ==> ONE_DIMM# */ + PAD_CFG_GPI(GPP_B16, NONE, PLTRST), + /* B17 : GPP_B17 ==> HOST_SD_WP# */ + PAD_CFG_GPO(GPP_B17, 0, PLTRST), + /* B18 : GPP_B18 ==> NRB_BIT (PIN STRAP, No Reboot) */ + PAD_NC(GPP_B18, NONE), + /* B19 : GPP_B19 ==> D3_RST# */ + PAD_CFG_GPO(GPP_B19, 0, DEEP), + /* B20 : GPP_B20 ==> LCD_CBL_DET# */ + PAD_CFG_GPI(GPP_B20, NONE, PLTRST), + /* B21 : GPP_B21 ==> PCH_TOUCH_SCREEN_EN */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + /* B22 : GPP_B22 ==> NC */ + PAD_NC(GPP_B22, NONE), + /* B23 : GPP_B23 ==> NC (PIN STRAP, CPUNSSC frequency) */ + PAD_NC(GPP_B23, NONE),
-/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { + /* C0 : GPP_C0 ==> MEM_SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : GPP_C1 ==> MEM_SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2 : GPP_C2 ==> NC (PIN STRAP, TLS Confidentiality) */ + PAD_NC(GPP_C2, NONE), + /* C3 : GPP_C3 ==> SML0_SMBCLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : GPP_C4 ==> SML0_SMBDATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : GPP_C5 ==> NC (PIN STRAP, Boot Strap 0) */ + PAD_NC(GPP_C5, NONE), + /* C6 : GPP_C6 ==> SML1_SMBCLK */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7 : GPP_C7 ==> SML1_SMBDATA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* C8 : GPP_C8 ==> WWAN_FULL_POWER_EN */ + PAD_CFG_GPO(GPP_C8, 1, DEEP), + /* C9 : GPP_C9 ==> SBIOS_TX */ + PAD_CFG_GPO(GPP_C9, 0, PLTRST), + /* C10 : GPP_C10 ==> NC */ + PAD_NC(GPP_C10, NONE), + /* C11 : GPP_C11 ==> NC */ + PAD_NC(GPP_C11, NONE), + /* C12 : GPP_C12 ==> NC */ + PAD_NC(GPP_C12, NONE), + /* C13 : GPP_C13 ==> PCH_SSD_PWR_EN */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C14 : GPP_C14 ==> NC */ + PAD_NC(GPP_C14, NONE), + /* C15 : GPP_C15 ==> NC */ + PAD_NC(GPP_C15, NONE), + /* C16 : GPP_C16 ==> I2C0_SDA_TS */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : GPP_C17 ==> I2C0_SCL_TS */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : GPP_C18 ==> I2C1_SDA_TP */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : GPP_C19 ==> I2C1_SCL_TP */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : GPP_C22 ==> H1_FLASH_WP */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* C23 : GPP_C23 ==> H1_PCH_INT# */ + PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT),
+ /* D0 : GPP_D0 ==> ISH_ACC1_INT */ + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + /* D1 : GPP_D1 ==> ISH_ACC2_INT */ + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + /* D2 : GPP_D2 ==> ISH_TABLE_MODE# */ + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + /* D3 : GPP_D3 ==> ISH_ALS_INT# */ + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + /* D4 : GPP_D4 ==> RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D5 : GPP_D5 ==> CLKREQ_PCIE#0 */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : GPP_D6 ==> CLKREQ_PCIE#1 */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : GPP_D7 ==> CLKREQ_PCIE#2 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : GPP_D8 ==> CLKREQ_PCIE#3 */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : GPP_D9 ==> TBT_2_LSX_TX */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + /* D10 : GPP_D10 ==> TBT_2_LSX_RX */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + /* D11 : GPP_D11 ==> TBT_3_LSX_TX */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), + /* D12 : GPP_D12 ==> TBT_3_LSX_RX */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF4), + /* D13 : GPP_D13 ==> SML0B_SMLDATA */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + /* D14 : GPP_D14 ==> SML0B_SMLCLK */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), + /* D15 : GPP_D15 ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : GPP_D16 ==> SML0BALERT# */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + /* D17 : GPP_D17 ==> ISH_NB_MODE# */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18 : GPP_D18 ==> ISH_LID_CL#_NB */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* D19 : GPP_D19 ==> NC */ + PAD_NC(GPP_D19, NONE), + + /* E0 : GPP_E0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : GPP_E1 ==> TOUCH_SCREEN_INT# */ + PAD_CFG_GPI_APIC(GPP_E1, NONE, PLTRST, LEVEL, INVERT), + /* E2 : GPP_E2 ==> MEDIACARD_IRQ# */ + PAD_CFG_GPI_APIC(GPP_E2, NONE, PLTRST, LEVEL, INVERT), + /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ + PAD_CFG_GPI(GPP_E3, NONE, PLTRST), + /* E4 : GPP_E4 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : GPP_E5 ==> M2280_DEVSLP */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : GPP_E6 ==> (PIN STRAP, Reserved) */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> PCH_TOUCHPAD_INTR# */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E7, NONE, PLTRST, LEVEL, INVERT), + /* E8 : GPP_E8 ==> SECURE_BIO */ + PAD_CFG_GPO(GPP_E8, 0, PLTRST), + /* E9 : GPP_E9 ==> OC0# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : GPP_E10 ==> HDMI_PD# */ + PAD_CFG_GPO(GPP_E10, 1, DEEP), + /* E11 : GPP_E11 ==> VPRO_DET# */ + PAD_CFG_GPI(GPP_E11, NONE, PLTRST), + /* E12 : GPP_E12 ==> RTC_DET# */ + PAD_CFG_GPI(GPP_E12, NONE, PLTRST), + /* E13 : GPP_E13 ==> TBT_DET# */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E14 : GPP_E14 ==> EPD_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : GPP_E15 ==> ISH_LID_CL#_TAB */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + /* E16 : GPP_E16 ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : GPP_E17 ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : GPP_E18 ==> TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : GPP_E19 ==> TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : GPP_E20 ==> TBT_LSX1_TXD */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : GPP_E21 ==> TBT_LSX1_RXD */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : GPP_E22 ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : GPP_E23 ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F0 : GPP_F0 ==> BRI_DT_1P8 */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : GPP_F1 ==> CNV_BRI_RSP_1P8 */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* F2 : GPP_F2 ==> CNV_RGI_DT_1P8 */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : GPP_F3 ==> CNV_RGI_RSP_1P8 */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* F4 : GPP_F4 ==> NC */ + PAD_NC(GPP_F4, NONE), + /* F5 : GPP_F5 ==> NC */ + PAD_NC(GPP_F5, NONE), + /* F6 : GPP_F6 ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F7 : GPP_F7 ==> NC (PIN STRAP, Reserved) */ + PAD_NC(GPP_F7, NONE), + /* F8 : GPP_F8 ==> NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : GPP_F9 ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPP_F10 ==> NC (PIN STRAP, Reserved) */ + PAD_NC(GPP_F10, NONE), + /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */ + PAD_CFG_GPI(GPP_F11, NONE, DEEP), + /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */ + PAD_CFG_GPI(GPP_F13, NONE, DEEP), + /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */ + PAD_CFG_GPI(GPP_F14, NONE, DEEP), + /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */ + PAD_CFG_GPI(GPP_F15, NONE, DEEP), + /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : GPP_F17 ==> WWAN_GPIO_PERST# */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* F18 : GPP_F18 ==> WWAN_GPIO_WAKE# */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : GPP_F19 ==> CAM_MIC_CBL_DET# */ + PAD_CFG_GPI(GPP_F19, NONE, PLTRST), + /* F20 : GPP_F20 ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : GPP_F21 ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), + /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ + PAD_CFG_GPI(GPP_H4, NONE, DEEP), + /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ + PAD_CFG_GPI(GPP_H5, NONE, DEEP), + /* H6 : GPP_H6 ==> SPK_DET1 */ + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), + /* H7 : GPP_H7 ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* H12 : GPP_H12 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13 ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14 ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : GPP_H15 ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : GPP_H16 ==> CPU_DPB_CTRL_CLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : GPP_H17 ==> CPU_DPB_CTRL_DATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : GPP_H19 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : GPP_H20 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : GPP_H21 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : GPP_H22 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : GPP_H23 ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R0 : GPP_R0 ==> HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* R1 : GPP_R1 ==> HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), + /* R2 : GPP_R2 ==> HDA_SDO (PIN STRAP, Flash Descriptor Security Override */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), + /* R3 : GPP_R3 ==> HDA_SDIO */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), + /* R4 : GPP_R4 ==> HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* R5 : GPP_R5 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : GPP_R6 ==> SD_PWR_EN1 */ + PAD_CFG_GPO(GPP_R6, 0, PLTRST), + /* R7 : GPP_R7 ==> SD_PWR_EN2 */ + PAD_CFG_GPO(GPP_R7, 0, PLTRST), + + /* S0 : GPP_S0 ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : GPP_S1 ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : GPP_S2 ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : GPP_S3 ==> NC */ + PAD_NC(GPP_S3, NONE), + /* S4 : GPP_S4 ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : GPP_S5 ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : GPP_S6 ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : GPP_S7 ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD0: GPD0 ==> PCH_BATLOW# */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: GPD1 ==> AC_PRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: GPD2 ==> LAN_WAKE# */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: GPD3 ==> SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + /* GPD4: GPD4 ==> SIO_SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: GPD5 ==> SIO_SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: GPD6 ==> SIO_SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7 ==> PCH_TBT_PERST# (PIN STRAP, Reserved) */ + PAD_CFG_GPO(GPD7, 0, PLTRST), + /* GPD8: GPD8 ==> SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: GPD9 ==> SIO_SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: GPD10 ==> SIO_SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: GPD11 ==> PM_LANPHY_EN */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), };
const struct pad_config *__weak variant_base_gpio_table(size_t *num) @@ -24,20 +406,47 @@ return gpio_table; }
-const struct pad_config *__weak variant_override_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} - -const struct pad_config *__weak variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} +/* GPIO pads configured in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A23 : GPP_A23 ==> RECOVERY# */ + PAD_CFG_GPI(GPP_A23, NONE, DEEP), + /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : GPP_C22 ==> H1_FLASH_WP */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* C23 : GPP_C23 ==> H1_PCH_INT# */ + PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT), + /* E3 : GPP_E3 ==> MEM_INTERLEAVED */ + PAD_CFG_GPI(GPP_E3, NONE, PLTRST), + /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */ + PAD_CFG_GPI(GPP_F11, NONE, DEEP), + /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */ + PAD_CFG_GPI(GPP_F13, NONE, DEEP), + /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */ + PAD_CFG_GPI(GPP_F14, NONE, DEEP), + /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */ + PAD_CFG_GPI(GPP_F15, NONE, DEEP), + /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */ + PAD_CFG_GPI(GPP_H4, NONE, DEEP), + /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */ + PAD_CFG_GPI(GPP_H5, NONE, DEEP), + /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* GPD3: GPD3 ==> SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +};
static const struct cros_gpio cros_gpios[] = { - + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_NAME), };
const struct cros_gpio *__weak variant_cros_gpios(size_t *num) @@ -45,3 +454,17 @@ *num = ARRAY_SIZE(cros_gpios); return cros_gpios; } + +/* Weak implementation of overrides */ +const struct pad_config *__weak variant_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +/* Weak implementation of early gpio */ +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index 8411900..e6092b6 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -4,10 +4,33 @@ * SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H
+#include <soc/gpe.h> #include <soc/gpio.h>
+/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_C22
-#endif /* BASEBOARD_GPIO_H */ +/* Recovery mode */ +#define GPIO_REC_MODE GPP_A23 + +/* DDR channel enable pin */ +#define DDR_CHA_EN GPP_H4 +#define DDR_CHB_EN GPP_H5 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F11 +#define GPIO_MEM_CONFIG_1 GPP_F12 +#define GPIO_MEM_CONFIG_2 GPP_F13 +#define GPIO_MEM_CONFIG_3 GPP_F14 +#define GPIO_MEM_CONFIG_4 GPP_F15 + + +const struct pad_config *override_gpio_table(size_t *num); +const struct pad_config *override_early_gpio_table(size_t *num); +struct cros_gpio; +const struct cros_gpio *override_cros_gpios(size_t *num); + +#endif
-
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