EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38665 )
Change subject: mb/google/drallion: Use GPP_D15 as touch reset pin ......................................................................
mb/google/drallion: Use GPP_D15 as touch reset pin
Follow HW change to use GPP_D15 as TS_RST.
BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 14 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38665/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 97860f4..ff5942b 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -336,9 +336,14 @@ register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.stop_delay_ms" = "20" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.stop_delay_ms" = "10" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" @@ -352,6 +357,9 @@ register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.stop_delay_ms" = "10" @@ -369,6 +377,8 @@ register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "10" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "stop_delay_ms" = "10" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index f2b7079..9666c2d 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -124,7 +124,7 @@ /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ /* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38665 )
Change subject: mb/google/drallion: Use GPP_D15 as touch reset pin ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38665/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38665/1/src/mainboard/google/dralli... PS1, Line 344: register "generic.stop_delay_ms" = "10" Please mention this change in the commit message too.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38665 )
Change subject: mb/google/drallion: Use GPP_D15 as touch reset pin ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38665/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38665/1/src/mainboard/google/dralli... PS1, Line 344: register "generic.stop_delay_ms" = "10"
Please mention this change in the commit message too.
This just correct aliment for 80 chars. Needed?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38665 )
Change subject: mb/google/drallion: Use GPP_D15 as touch reset pin ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38665/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38665/1/src/mainboard/google/dralli... PS1, Line 344: register "generic.stop_delay_ms" = "10"
This just correct aliment for 80 chars. […]
Oh, this stop delay is miss. I will recover it.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38665
to look at the new patch set (#2).
Change subject: mb/google/drallion: Use GPP_D15 as touch reset pin ......................................................................
mb/google/drallion: Use GPP_D15 as touch reset pin
Follow HW change to use GPP_D15 as TS_RST.
BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 13 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38665/2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38665 )
Change subject: mb/google/drallion: Use GPP_D15 as touch reset pin ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38665/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38665/1/src/mainboard/google/dralli... PS1, Line 344: register "generic.stop_delay_ms" = "10"
Oh, this stop delay is miss. I will recover it.
Done
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38665
to look at the new patch set (#3).
Change subject: mb/google/drallion: Use GPP_D15 as touch reset pin ......................................................................
mb/google/drallion: Use GPP_D15 as touch reset pin
Follow HW change to use GPP_D15 as TS_RST.
BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 17 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38665/3
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38665 )
Change subject: mb/google/drallion: Use GPP_D15 as touch reset pin ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38665/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/38665/3/src/mainboard/google/dralli... PS3, Line 81: /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */ TBD change
Hello Mathew King, Roy Mingi Park, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38665
to look at the new patch set (#4).
Change subject: mb/google/drallion: Fine tune touch screen power sequence ......................................................................
mb/google/drallion: Fine tune touch screen power sequence
Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst to deep in order to met power off timing.
BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 17 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38665/4
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38665 )
Change subject: mb/google/drallion: Fine tune touch screen power sequence ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38665 )
Change subject: mb/google/drallion: Fine tune touch screen power sequence ......................................................................
mb/google/drallion: Fine tune touch screen power sequence
Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst to deep in order to met power off timing.
BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665 Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 17 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 97860f4..06d3e5d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -336,9 +336,15 @@ register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "5" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.stop_delay_ms" = "20" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" @@ -352,6 +358,10 @@ register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "5" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.stop_delay_ms" = "10" @@ -369,6 +379,9 @@ register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "5" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "stop_delay_ms" = "10" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index f2b7079..1c864ca 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -78,7 +78,7 @@ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* PCH_3.3V_TS_EN */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),
@@ -124,7 +124,7 @@ /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ /* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
-
Duncan Laurie (Code Review) -
EricR Lai (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)