Change in coreboot[master]: soc/intel/tigerlake: Fix build issues

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 )

Change subject: soc/intel/tigerlake: Fix build issues
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37426/5/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/romstage.h:

https://review.coreboot.org/c/coreboot/+/37426/5/src/soc/intel/tigerlake/inc... 
PS5, Line 21: void mainboard_fspm_params(FSPM_UPD *mupd);
need consistent spacing around '*' (ctx:WxV)