Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33818
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
Update FSP header files with 7.0.64.40 version for Cannonlake platform.
Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h 4 files changed, 6,400 insertions(+), 6,381 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33818/1
Bora Guvendik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
Update FSP header files with 7.0.64.40 version for Cannonlake platform.
Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h 3 files changed, 6,440 insertions(+), 6,333 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33818/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33818
to look at the new patch set (#3).
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
Update FSP header files with 7.0.64.40 version for Cannonlake platform.
Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 2 files changed, 176 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33818/3
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/33818/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33818/3//COMMIT_MSG@10 PS3, Line 10: Please add a summary of the changes (change-log).
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33818
to look at the new patch set (#4).
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
Update FSP header files with 7.0.64.40 version for Cannonlake platform, the following changes were made, Silicon Init UPD: 1. Add UPD to disable Heci1. 2. Add CD clock selections of 675MHz. 3. Add UPD to program GT Chicken bits. 4. Add various xHCI USB related UPDs. 5. Teton Glacier Cycle Router UPD deprecated. 6. CdynmaxClampEnable is enabled by default now. 7. Add UPDs for C3 Cstate Demotion. Memory Init UPD: 1. Add GDXC configuration options. 2. Remove some internal graphics memory selections. 3. Remove Fixed mid option for SaGv. 4. Add DualDimm per channel board type. 5. Add UPD for DDR4 mixed U-DIMM 2DPC Limitation. 6. Add UPD to skip DDR4 refresh. 7. Add UPD for Lpddr Dram Odt.
Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 2 files changed, 176 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33818/4
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 4:
(1 comment)
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/33818/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33818/3//COMMIT_MSG@10 PS3, Line 10:
Please add a summary of the changes (change-log).
Done
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 4: Code-Review+2
Hello Subrata Banik, Selma Bensaid, Duncan Laurie, Lijian Zhao, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33818
to look at the new patch set (#5).
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
Update FSP header files with 7.0.64.40 version for Cannonlake platform, the following changes were made, Silicon Init UPD: 1. Add UPD to disable Heci1. 2. Add CD clock selections of 675MHz. 3. Add UPD to program GT Chicken bits. 4. Add various xHCI USB related UPDs. 5. Teton Glacier Cycle Router UPD deprecated. 6. CdynmaxClampEnable is enabled by default now. 7. Add UPDs for C3 Cstate Demotion. Memory Init UPD: 1. Add GDXC configuration options. 2. Remove some internal graphics memory selections. 3. Remove Fixed mid option for SaGv. 4. Add DualDimm per channel board type. 5. Add UPD for DDR4 mixed U-DIMM 2DPC Limitation. 6. Add UPD to skip DDR4 refresh. 7. Add UPD for Lpddr Dram Odt.
Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 2 files changed, 176 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33818/5
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 5: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 5:
(2 comments)
Looks good, but there's two things that look odd to me.
https://review.coreboot.org/#/c/33818/5/src/vendorcode/intel/fsp/fsp2_0/cann... File src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h:
https://review.coreboot.org/#/c/33818/5/src/vendorcode/intel/fsp/fsp2_0/cann... PS5, Line 2298: : : : : : : : : : : : : : : : This change is not listed in the commit message
https://review.coreboot.org/#/c/33818/5/src/vendorcode/intel/fsp/fsp2_0/cann... File src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h:
https://review.coreboot.org/#/c/33818/5/src/vendorcode/intel/fsp/fsp2_0/cann... PS5, Line 853: Chickent Chicken
Hello Subrata Banik, Selma Bensaid, Duncan Laurie, build bot (Jenkins), Lijian Zhao, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33818
to look at the new patch set (#6).
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
Update FSP header files with 7.0.64.40 version for Cannonlake platform, the following changes were made, Silicon Init UPD: 1. Add UPD to disable Heci1. 2. Add CD clock selections of 675MHz. 3. Add UPD to program GT Chicken bits. 4. Add various xHCI USB related UPDs. 5. Teton Glacier Cycle Router UPD deprecated. 6. CdynmaxClampEnable is enabled by default now. 7. Add UPDs for C3 Cstate Demotion. Memory Init UPD: 1. Add GDXC configuration options. 2. Remove some internal graphics memory selections. 3. Remove Fixed mid option for SaGv. 4. Add DualDimm per channel board type. 5. Add UPD for DDR4 mixed U-DIMM 2DPC Limitation. 6. Add UPD to skip DDR4 refresh. 7. Add UPD for Lpddr Dram Odt. 8. Remove PEG IMR options.
Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 2 files changed, 176 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33818/6
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/#/c/33818/5/src/vendorcode/intel/fsp/fsp2_0/cann... File src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h:
https://review.coreboot.org/#/c/33818/5/src/vendorcode/intel/fsp/fsp2_0/cann... PS5, Line 2298: : : : : : : : : : : : : : : :
This change is not listed in the commit message
Done
https://review.coreboot.org/#/c/33818/5/src/vendorcode/intel/fsp/fsp2_0/cann... File src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h:
https://review.coreboot.org/#/c/33818/5/src/vendorcode/intel/fsp/fsp2_0/cann... PS5, Line 853: Chickent
Chicken
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
No idea, if the typos should be fixed upstream to not diverge.
https://review.coreboot.org/#/c/33818/6/src/vendorcode/intel/fsp/fsp2_0/cann... File src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h:
https://review.coreboot.org/#/c/33818/6/src/vendorcode/intel/fsp/fsp2_0/cann... PS6, Line 854: Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] Program
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 6:
Patch Set 6: Code-Review+1
(1 comment)
No idea, if the typos should be fixed upstream to not diverge.
Ideally, I think it would be good to fix the typos upstream. Less divergence would make it easy to sync in the future.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Patch Set 6: Code-Review+1
Patch Set 6:
Patch Set 6: Code-Review+1
(1 comment)
No idea, if the typos should be fixed upstream to not diverge.
Ideally, I think it would be good to fix the typos upstream. Less divergence would make it easy to sync in the future.
I agree.
Bora Guvendik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33818 )
Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake ......................................................................
Abandoned