New subject: Change in libgfxinit[master]: [WIP] gma: Add Gemini Lake support

25 Feb 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611
Change subject: [WIP] gma: Add Gemini Lake support
......................................................................
[WIP] gma: Add Gemini Lake support
Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d
Signed-off-by: Nico Huber nico.huber@secunet.com
---
M common/Makefile.inc
M common/broxton/hw-gfx-gma-ddi_phy.ads
M common/broxton/hw-gfx-gma-plls.adb
M common/broxton/hw-gfx-gma-power_and_clocks.adb
M common/hw-gfx-gma-config.ads.template
M common/hw-gfx-gma-registers.ads
M common/hw-gfx-gma.ads
R configs/apollolake
C configs/geminilake
9 files changed, 109 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1

diff --git a/common/Makefile.inc b/common/Makefile.inc
index 61955eb..cfb2dfa 100644
--- a/common/Makefile.inc
+++ b/common/Makefile.inc
@@ -68,7 +68,7 @@
 subdirs-y += ironlake
 else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),)
 subdirs-y += haswell_shared haswell
-else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),)
+else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),)
 subdirs-y += haswell_shared broxton
 else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),)
 subdirs-y += haswell_shared skylake
diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads
index fc6cacf..e6301bf 100644
--- a/common/broxton/hw-gfx-gma-ddi_phy.ads
+++ b/common/broxton/hw-gfx-gma-ddi_phy.ads
@@ -16,7 +16,7 @@
private package HW.GFX.GMA.DDI_Phy is
-   type T is (BC, A);
+   type T is (BC, A, C);
procedure Power_On (Phy : T);
    procedure Power_Off (Phy : T);
diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb
index 087ff12..f7ecc05 100644
--- a/common/broxton/hw-gfx-gma-plls.adb
+++ b/common/broxton/hw-gfx-gma-plls.adb
@@ -170,6 +170,8 @@
       PLL_10         : Registers_Index;
       PCS_DW12_LN01  : Registers_Index;
       PCS_DW12_GRP   : Registers_Index;
+      TX_DW5_LN0     : Registers_Index;
+      TX_DW5_GRP     : Registers_Index;
    end record;
    type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs;
@@ -187,7 +189,9 @@
          PLL_9          => BXT_PORT_PLL_9_A,
          PLL_10         => BXT_PORT_PLL_10_A,
          PCS_DW12_LN01  => BXT_PORT_PCS_DW12_01_A,
-         PCS_DW12_GRP   => BXT_PORT_PCS_DW12_GRP_A),
+         PCS_DW12_GRP   => BXT_PORT_PCS_DW12_GRP_A,
+         TX_DW5_LN0     => BXT_PORT_TX_DW5_LN0_A,
+         TX_DW5_GRP     => BXT_PORT_TX_DW5_GRP_A),
       DPLL_B =>
         (PLL_ENABLE     => BXT_PORT_PLL_ENABLE_B,
          PLL_EBB_0      => BXT_PORT_PLL_EBB_0_B,
@@ -201,7 +205,9 @@
          PLL_9          => BXT_PORT_PLL_9_B,
          PLL_10         => BXT_PORT_PLL_10_B,
          PCS_DW12_LN01  => BXT_PORT_PCS_DW12_01_B,
-         PCS_DW12_GRP   => BXT_PORT_PCS_DW12_GRP_B),
+         PCS_DW12_GRP   => BXT_PORT_PCS_DW12_GRP_B,
+         TX_DW5_LN0     => BXT_PORT_TX_DW5_LN0_B,
+         TX_DW5_GRP     => BXT_PORT_TX_DW5_GRP_B),
       DPLL_C =>
         (PLL_ENABLE     => BXT_PORT_PLL_ENABLE_C,
          PLL_EBB_0      => BXT_PORT_PLL_EBB_0_C,
@@ -215,11 +221,15 @@
          PLL_9          => BXT_PORT_PLL_9_C,
          PLL_10         => BXT_PORT_PLL_10_C,
          PCS_DW12_LN01  => BXT_PORT_PCS_DW12_01_C,
-         PCS_DW12_GRP   => BXT_PORT_PCS_DW12_GRP_C));
+         PCS_DW12_GRP   => BXT_PORT_PCS_DW12_GRP_C,
+         TX_DW5_LN0     => BXT_PORT_TX_DW5_LN0_C,
+         TX_DW5_GRP     => BXT_PORT_TX_DW5_GRP_C));
PORT_PLL_ENABLE                     : constant :=      1 * 2 ** 31;
    PORT_PLL_ENABLE_LOCK                : constant :=      1 * 2 ** 30;
    PORT_PLL_ENABLE_REF_SEL             : constant :=      1 * 2 ** 27;
+   PORT_PLL_POWER_ENABLE               : constant :=      1 * 2 ** 26;
+   PORT_PLL_POWER_STATE                : constant :=      1 * 2 ** 25;
PORT_PLL_EBB0_P1_SHIFT              : constant :=               13;
    PORT_PLL_EBB0_P1_MASK               : constant := 16#07# * 2 ** 13;
@@ -336,8 +346,17 @@
    begin
       pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
-      Set_Mask    (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL);   -- non-SSC ref
-      Unset_Mask  (PORT (P).PLL_EBB_4,  PORT_PLL_EBB4_10BIT_CLK_ENABLE);
+      Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL);   -- non-SSC ref
+
+      if Config.Has_Port_PLL_Pwr_En then
+         Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE);
+         Wait_Set_Mask
+           (Register => PORT (P).PLL_ENABLE,
+            Mask     => PORT_PLL_POWER_STATE,
+            TOut_MS  => 1);   -- 200us
+      end if;
+
+      Unset_Mask (PORT (P).PLL_EBB_4,  PORT_PLL_EBB4_10BIT_CLK_ENABLE);
Unset_And_Set_Mask
         (Register    => PORT (P).PLL_EBB_0,
@@ -388,7 +407,16 @@
       Wait_Set_Mask
         (Register => PORT (P).PLL_ENABLE,
          Mask     => PORT_PLL_ENABLE_LOCK,
-         TOut_MS  => 1);   -- 100us
+         TOut_MS  => 1);   -- 200us
+
+      if (Config.Has_DCC_Delay_Range) then
+         declare
+            Delay_Range : Word32;
+         begin
+            Read (PORT (P).DW5_LN0, Delay_Range);
+            Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2;
+            Write (PORT (P).DW5_GRP, Delay_Range);
+      end if;
Read (PORT (P).PCS_DW12_LN01, PCS);
       PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK;
@@ -471,6 +499,13 @@
    begin
       if PLL in Valid_PLLs then
          Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE);
+         if Config.Has_Port_PLL_Pwr_En then
+            Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE);
+            Wait_Unset_Mask
+              (Register => PORT (P).PLL_ENABLE,
+               Mask     => PORT_PLL_POWER_STATE,
+               TOut_MS  => 1);   -- 200us
+         end if;
       end if;
    end Free;
diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb
index 8aa9a21..4e3fbc3 100644
--- a/common/broxton/hw-gfx-gma-power_and_clocks.adb
+++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb
@@ -214,22 +214,12 @@
----------------------------------------------------------------------------
-   CDClk_Ref : constant := 19_200_000;
-
    procedure Set_CDClk (Freq : Frequency_Type)
    with
-      Pre =>
-         Freq =   CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or
-         Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000
+      Pre => Config.Valid_CDClk (Freq)
    is
       VCO : constant Int64 :=
-         CDClk_Ref *
-           (if Freq = CDClk_Ref then
-               0
-            elsif Freq = 624_000_000 then
-               65
-            else
-               60);
+         Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq);
       CDCLK_CD2X_Div_Sel : constant Word32 :=
         (case VCO / Freq is   -- CDClk = VCO / 2 / Div
             when 2      => CDCLK_CD2X_DIV_SEL_1,
@@ -255,7 +245,8 @@
       Unset_And_Set_Mask
         (Register    => BXT_DE_PLL_CTL,
          Mask_Unset  => BXT_DE_PLL_RATIO_MASK,
-         Mask_Set    => Word32 (VCO / CDClk_Ref));
+         Mask_Set    => (if Freq = Config.Broxton_CDClk_Ref then 0 else
+                           Word32 (VCO / Config.Broxton_CDClk_Ref)));
       Write
         (Register => BXT_DE_PLL_ENABLE,
          Value    => BXT_DE_PLL_PLL_ENABLE);
@@ -297,7 +288,7 @@
-- Linux' i915 never keeps the PLL disabled but runs it
       -- at a "ratio" of 0 with CDClk at its reference clock.
-      Set_CDClk (CDClk_Ref);
+      Set_CDClk (Config.Broxton_CDClk_Ref);
PW_Off (PW1);
    end Post_All_Off;
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index 4653ae9..972cfa8 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -40,7 +40,8 @@
    Has_Internal_Display    : constant Boolean := Internal_Display /= None;
    Internal_Is_EDP         : constant Boolean := Internal_Display = DP;
    Have_DVI_I              : constant Boolean := Analog_I2C_Port /= PCH_DAC;
-   Has_Presence_Straps     : constant Boolean := CPU /= Broxton;
+   Is_Broxton              : constant Boolean := CPU in Apollolake..Geminilake;
+   Has_Presence_Straps     : constant Boolean := not Is_Broxton;
    Is_ULT                  : constant Boolean := CPU_Var = ULT;
    Is_ULX                  : constant Boolean := CPU_Var = ULX;
    Is_LP                   : constant Boolean := Is_ULT or Is_ULX;
@@ -57,7 +58,7 @@
    Has_Pipe_MSA_Misc       : constant Boolean := CPU >= Haswell;
    Has_Pipeconf_Misc       : constant Boolean := CPU >= Broadwell;
    Has_Pipeconf_BPC        : constant Boolean := CPU /= Haswell;
-   Has_Plane_Control       : constant Boolean := CPU >= Broxton;
+   Has_Plane_Control       : constant Boolean := CPU >= Apollolake;
    Has_DSP_Linoff          : constant Boolean := CPU <= Ivybridge;
    Has_PF_Pipe_Select      : constant Boolean := CPU in Ivybridge .. Haswell;
    Has_Cursor_FBC_Control  : constant Boolean := CPU >= Ivybridge;
@@ -73,7 +74,7 @@
    Has_PCH_Panel_Power     : constant Boolean := CPU >= Ironlake;
----- PCH/FDI: ---------
-   Has_PCH                 : constant Boolean := CPU /= Broxton and CPU /= G45;
+   Has_PCH                 : constant Boolean := not Is_Broxton and CPU /= G45;
    Has_PCH_DAC             : constant Boolean := CPU in Ironlake .. Ivybridge or
                                                  (CPU in Haswell .. Broadwell
                                                   and not Is_LP);
@@ -103,7 +104,9 @@
                                                   and Is_LP) or
                                                  CPU >= Skylake;
-   Has_DDI_PHYs            : constant Boolean := CPU = Broxton;
+   Has_DDI_PHYs            : constant Boolean := Is_Broxton;
+   Has_Dual_DDI_Phy_BC     : constant Boolean := CPU = Apollolake;
+   Has_Port_PLL_Pwr_En     : constant Boolean := CPU = Geminilake;
Has_DDI_D               : constant Boolean := CPU >= Haswell and
                                                  not Is_LP and
@@ -112,8 +115,8 @@
                                                  Has_DDI_D;
Has_DDI_Buffer_Trans    : constant Boolean := CPU >= Haswell and
-                                                 CPU /= Broxton;
-   Has_Low_Voltage_Swing   : constant Boolean := CPU >= Broxton;
+                                                 not Is_Broxton;
+   Has_Low_Voltage_Swing   : constant Boolean := CPU >= Apollolake;
    Has_Iboost_Config       : constant Boolean := CPU >= Skylake;
    Use_KBL_DDI_Buf_Trans   : constant Boolean := CPU = Kabylake;
@@ -126,7 +129,7 @@
----- GMBUS: -----------
    Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake;
-   GMBUS_Alternative_Pins  : constant Boolean := CPU = Broxton;
+   GMBUS_Alternative_Pins  : constant Boolean := Is_Broxton;
    Has_PCH_GMBUS           : constant Boolean := CPU >= Ironlake;
----- Power: -----------
@@ -178,7 +181,8 @@
          DP3      => CPU_Var = Normal,
          Analog   => CPU_Var = Normal,
          others   => True),
-      Broxton     =>
+      Apollolake  |
+      Geminilake  =>
         (Internal => Config.Internal_Display = DP,
          DP1      => True,
          DP2      => True,
@@ -234,11 +238,12 @@
Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range :=
      (case CPU is
-         when Haswell   => 6,
-         when Broadwell => 7,
-         when Broxton   => 8,
-         when Skylake   => 8,
-         when others    => 0);
+         when Haswell      => 6,
+         when Broadwell    => 7,
+         when Apollolake   |
+              Geminilake   => 8,
+         when Skylake      => 8,
+         when others       => 0);
----------------------------------------------------------------------------
@@ -250,7 +255,8 @@
               Ivybridge    => 400_000_000,
          when Haswell      |
               Broadwell    => (if Is_ULX then 337_500_000 else 450_000_000),
-         when Broxton      => 288_000_000,
+         when Apollolake   => 288_000_000,
+         when Geminilake   => 158_400_000,
          when Skylake      |
               Kabylake     => 337_500_000);
@@ -262,13 +268,34 @@
               Ivybridge    => 125_000_000,
          when Haswell      |
               Broadwell    => (if Is_LP then  24_000_000 else 125_000_000),
-         when Broxton      => Frequency_Type'First,   -- none needed
+         when Apollolake   |
+              Geminilake   => Frequency_Type'First,   -- none needed
          when Skylake      |
               Kabylake     => 24_000_000);
Raw_Clock : Frequency_Type := Default_RawClk_Freq
     with Part_Of => GMA.Config_State;
+   Broxton_CDClk_Ref : constant := 19_200_000;
+
+   function Valid_CDClk (Freq : Frequency_Type) return Boolean is
+     (case CPU is
+         when Geminilake =>
+            Freq = Broxton_CDClk_Ref or Freq =  79_200_000 or
+            Freq =       158_400_000 or Freq = 316_800_000,
+         when Apollolake =>
+            Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or
+            Freq =       288_000_000 or Freq = 384_000_000 or
+            Freq =       576_000_000 or Freq = 624_000_000,
+         when others =>
+            True);
+
+   function CDClk_Ratio (Freq : Frequency_Type) return Int64 is
+     (case CPU is
+         when Geminilake   => 33,
+         when Apollolake   => if Freq = 624_000_000 then 65 else 60,
+         when others       => 1);
+
    ----------------------------------------------------------------------------
-- Maximum source width with enabled scaler. This only accounts
@@ -414,7 +441,8 @@
                                  when Normal => Is_Broadwell (Device_Id),
                                  when ULT    => Is_Broadwell_U (Device_Id),
                                  when ULX    => Is_Broadwell_Y (Device_Id)),
-         when Broxton      => (Device_Id and 16#fffe#) = 16#5a84#,
+         when Apollolake   => (Device_Id and 16#fffe#) = 16#5a84#,
+         when Geminilake   => (Device_Id and 16#fffe#) = 16#3184#,
          when Skylake      => (case CPU_Var is
                                  when Normal => Is_Skylake (Device_Id),
                                  when ULT    => Is_Skylake_U (Device_Id),
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 1220d1a..b14194b 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -413,6 +413,7 @@
       BXT_PORT_TX_DW2_LN0_B,
       BXT_PORT_TX_DW3_LN0_B,
       BXT_PORT_TX_DW4_LN0_B,
+      BXT_PORT_TX_DW5_LN0_B,
       BXT_PORT_TX_DW14_LN0_B,
       BXT_PORT_TX_DW14_LN1_B,
       BXT_PORT_TX_DW14_LN2_B,
@@ -422,6 +423,7 @@
       BXT_PORT_TX_DW2_LN0_C,
       BXT_PORT_TX_DW3_LN0_C,
       BXT_PORT_TX_DW4_LN0_C,
+      BXT_PORT_TX_DW5_LN0_C,
       BXT_PORT_TX_DW14_LN0_C,
       BXT_PORT_TX_DW14_LN1_C,
       BXT_PORT_TX_DW14_LN2_C,
@@ -431,11 +433,13 @@
       BXT_PORT_TX_DW2_GRP_B,
       BXT_PORT_TX_DW3_GRP_B,
       BXT_PORT_TX_DW4_GRP_B,
+      BXT_PORT_TX_DW5_GRP_B,
       BXT_PORT_PCS_DW10_GRP_C,
       BXT_PORT_PCS_DW12_GRP_C,
       BXT_PORT_TX_DW2_GRP_C,
       BXT_PORT_TX_DW3_GRP_C,
       BXT_PORT_TX_DW4_GRP_C,
+      BXT_PORT_TX_DW5_GRP_C,
       BXT_DE_PLL_CTL,
       HTOTAL_EDP,
       HBLANK_EDP,
@@ -722,6 +726,7 @@
       BXT_PORT_TX_DW2_LN0_A,
       BXT_PORT_TX_DW3_LN0_A,
       BXT_PORT_TX_DW4_LN0_A,
+      BXT_PORT_TX_DW5_LN0_A,
       BXT_PORT_TX_DW14_LN0_A,
       BXT_PORT_TX_DW14_LN1_A,
       BXT_PORT_TX_DW14_LN2_A,
@@ -730,7 +735,8 @@
       BXT_PORT_PCS_DW12_GRP_A,
       BXT_PORT_TX_DW2_GRP_A,
       BXT_PORT_TX_DW3_GRP_A,
-      BXT_PORT_TX_DW4_GRP_A);
+      BXT_PORT_TX_DW4_GRP_A,
+      BXT_PORT_TX_DW5_GRP_A);
pragma Warnings
      (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
@@ -1351,6 +1357,7 @@
       BXT_PORT_TX_DW2_LN0_A   => 16#16_2508# / Register_Width,
       BXT_PORT_TX_DW3_LN0_A   => 16#16_250c# / Register_Width,
       BXT_PORT_TX_DW4_LN0_A   => 16#16_2510# / Register_Width,
+      BXT_PORT_TX_DW5_LN0_A   => 16#16_2514# / Register_Width,
       BXT_PORT_TX_DW14_LN0_A  => 16#16_2538# / Register_Width,
       BXT_PORT_TX_DW14_LN1_A  => 16#16_25b8# / Register_Width,
       BXT_PORT_TX_DW14_LN2_A  => 16#16_2738# / Register_Width,
@@ -1358,9 +1365,11 @@
       BXT_PORT_TX_DW2_GRP_A   => 16#16_2d08# / Register_Width,
       BXT_PORT_TX_DW3_GRP_A   => 16#16_2d0c# / Register_Width,
       BXT_PORT_TX_DW4_GRP_A   => 16#16_2d10# / Register_Width,
+      BXT_PORT_TX_DW5_GRP_A   => 16#16_2d14# / Register_Width,
       BXT_PORT_TX_DW2_LN0_B   => 16#06_c508# / Register_Width,
       BXT_PORT_TX_DW3_LN0_B   => 16#06_c50c# / Register_Width,
       BXT_PORT_TX_DW4_LN0_B   => 16#06_c510# / Register_Width,
+      BXT_PORT_TX_DW5_LN0_B   => 16#06_c514# / Register_Width,
       BXT_PORT_TX_DW14_LN0_B  => 16#06_c538# / Register_Width,
       BXT_PORT_TX_DW14_LN1_B  => 16#06_c5b8# / Register_Width,
       BXT_PORT_TX_DW14_LN2_B  => 16#06_c738# / Register_Width,
@@ -1368,9 +1377,11 @@
       BXT_PORT_TX_DW2_GRP_B   => 16#06_cd08# / Register_Width,
       BXT_PORT_TX_DW3_GRP_B   => 16#06_cd0c# / Register_Width,
       BXT_PORT_TX_DW4_GRP_B   => 16#06_cd10# / Register_Width,
+      BXT_PORT_TX_DW5_GRP_B   => 16#06_cd14# / Register_Width,
       BXT_PORT_TX_DW2_LN0_C   => 16#06_c908# / Register_Width,
       BXT_PORT_TX_DW3_LN0_C   => 16#06_c90c# / Register_Width,
       BXT_PORT_TX_DW4_LN0_C   => 16#06_c910# / Register_Width,
+      BXT_PORT_TX_DW5_LN0_C   => 16#06_c914# / Register_Width,
       BXT_PORT_TX_DW14_LN0_C  => 16#06_c938# / Register_Width,
       BXT_PORT_TX_DW14_LN1_C  => 16#06_c9b8# / Register_Width,
       BXT_PORT_TX_DW14_LN2_C  => 16#06_cb38# / Register_Width,
@@ -1378,6 +1389,7 @@
       BXT_PORT_TX_DW2_GRP_C   => 16#06_cf08# / Register_Width,
       BXT_PORT_TX_DW3_GRP_C   => 16#06_cf0c# / Register_Width,
       BXT_PORT_TX_DW4_GRP_C   => 16#06_cf10# / Register_Width,
+      BXT_PORT_TX_DW5_GRP_C   => 16#06_cf14# / Register_Width,
-- Broxton DDI PHY ref registers
       BXT_PORT_REF_DW3_A      => 16#16_218c# / Register_Width,
diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads
index 7ca0ca1..c282935 100644
--- a/common/hw-gfx-gma.ads
+++ b/common/hw-gfx-gma.ads
@@ -41,7 +41,8 @@
       Ivybridge,
       Haswell,
       Broadwell,
-      Broxton,
+      Apollolake,
+      Geminilake,
       Skylake,
       Kabylake);
diff --git a/configs/broxton b/configs/apollolake
similarity index 83%
rename from configs/broxton
rename to configs/apollolake
index b5f1f9a..24e0847 100644
--- a/configs/broxton
+++ b/configs/apollolake
@@ -1,4 +1,4 @@
-CONFIG_GFX_GMA_CPU		= Broxton
+CONFIG_GFX_GMA_CPU		= Apollolake
 CONFIG_GFX_GMA_CPU_VARIANT	= Normal	# N/A
 CONFIG_GFX_GMA_INTERNAL_PORT	= DP
 CONFIG_GFX_GMA_ANALOG_I2C_PORT	= PCH_DAC	# N/A
diff --git a/configs/broxton b/configs/geminilake
similarity index 83%
copy from configs/broxton
copy to configs/geminilake
index b5f1f9a..be34de7 100644
--- a/configs/broxton
+++ b/configs/geminilake
@@ -1,4 +1,4 @@
-CONFIG_GFX_GMA_CPU		= Broxton
+CONFIG_GFX_GMA_CPU		= Geminilake
 CONFIG_GFX_GMA_CPU_VARIANT	= Normal	# N/A
 CONFIG_GFX_GMA_INTERNAL_PORT	= DP
 CONFIG_GFX_GMA_ANALOG_I2C_PORT	= PCH_DAC	# N/A
-- 
To view, visit https://review.coreboot.org/c/libgfxinit/+/31611
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Gerrit-Project: libgfxinit
Gerrit-Branch: master
Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d
Gerrit-Change-Number: 31611
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber nico.h@gmx.de
Gerrit-MessageType: newchange



    

Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support