Attention is currently required from: Furquan Shaikh, Scott Chao.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56715 )
Change subject: mb/google/brya/variants/gimble: add TcssAuxOri
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Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/gimble/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/56715/comment/203a5e60_7e04df5b
PS1, Line 23: register "TcssAuxOri" = "1"
Without a retimer on port 0, I think you will also need to do the following:
1) Ensure the GPIOs used for AUX biasing on port 0 are programmed as NF6 (looks like GPP_E22 and GPP_E23 ?)
2) Add the following to the devicetree; this lets the SoC IOM firmware control the Aux DC bias voltages:
`register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"`
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