Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
util: Add new memory part for zork boards
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets.
BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- A src/mainboard/google/zork/spd/ddr4-spd-9.hex M src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt A src/soc/intel/tigerlake/spd/ddr4-spd-9.hex M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt 5 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45647/1
diff --git a/src/mainboard/google/zork/spd/ddr4-spd-9.hex b/src/mainboard/google/zork/spd/ddr4-spd-9.hex new file mode 100644 index 0000000..a67d756 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 86 29 91 08 00 00 00 00 01 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt index 13de1cd..bb4080d 100644 --- a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt +++ b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt @@ -12,3 +12,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-9.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex new file mode 100644 index 0000000..a67d756 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 86 29 91 08 00 00 00 00 01 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt index 13de1cd..bb4080d 100644 --- a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt @@ -12,3 +12,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-9.hex diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt index 2f4bc8e..fdfe938 100644 --- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt +++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt @@ -179,6 +179,18 @@ "TRFC2MinPs": 260000, "TRFC4MinPs": 160000 } + }, + { + // Datasheet Revision: Rev. 1.0, Feb. 2020 + "name": "H5ANAG6NDMR-XNC", + "attribs": { + "speedMTps": 3200, + "CL_nRCD_nRP": 22, + "capacityPerDieGb": 16, + "diesPerPackage": 2, + "packageBusWidth": 16, + "ranksPerPackage": 1 + } } ] }
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 1: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45647/1/util/spd_tools/ddr4/global_... File util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/45647/1/util/spd_tools/ddr4/global_... PS1, Line 189: "capacityPerDieGb": 16, The capacity per die should be 8Gb. It's a 2 die package, so 8Gb x 2 die = 16Gb. This is identical to H5ANAG6NCMR-XNC above, just generation 5 instead of 4.
Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Tim Wawrzynczak, Nick Vaccaro, Rob Barnes, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45647
to look at the new patch set (#2).
Change subject: util: Add new memory part for zork boards ......................................................................
util: Add new memory part for zork boards
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets.
BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt 3 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45647/2
Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45647/1/util/spd_tools/ddr4/global_... File util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/45647/1/util/spd_tools/ddr4/global_... PS1, Line 189: "capacityPerDieGb": 16,
The capacity per die should be 8Gb. It's a 2 die package, so 8Gb x 2 die = 16Gb. […]
Done. Thanks for your review.
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 2: Code-Review+1
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45647/1/util/spd_tools/ddr4/global_... File util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/45647/1/util/spd_tools/ddr4/global_... PS1, Line 189: "capacityPerDieGb": 16,
Done. […]
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45647/2/util/spd_tools/ddr4/global_... File util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/45647/2/util/spd_tools/ddr4/global_... PS2, Line 183: no tab here to match the other entries.
Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Tim Wawrzynczak, Nick Vaccaro, Rob Barnes, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45647
to look at the new patch set (#3).
Change subject: util: Add new memory part for zork boards ......................................................................
util: Add new memory part for zork boards
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets.
BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt 3 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45647/3
Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45647/2/util/spd_tools/ddr4/global_... File util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/45647/2/util/spd_tools/ddr4/global_... PS2, Line 183:
no tab here to match the other entries.
Done.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45647/2/util/spd_tools/ddr4/global_... File util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/45647/2/util/spd_tools/ddr4/global_... PS2, Line 183:
Done.
Done
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45647 )
Change subject: util: Add new memory part for zork boards ......................................................................
util: Add new memory part for zork boards
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets.
BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt 3 files changed, 14 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt index 13de1cd..202f173 100644 --- a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt +++ b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt @@ -12,3 +12,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-2.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt index 13de1cd..202f173 100644 --- a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt @@ -12,3 +12,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-2.hex diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt index 2f4bc8e..776bce7 100644 --- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt +++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt @@ -179,6 +179,18 @@ "TRFC2MinPs": 260000, "TRFC4MinPs": 160000 } + }, + { + // Datasheet Revision: Rev. 1.0, Feb. 2020 + "name": "H5ANAG6NDMR-XNC", + "attribs": { + "speedMTps": 3200, + "CL_nRCD_nRP": 22, + "capacityPerDieGb": 8, + "diesPerPackage": 2, + "packageBusWidth": 16, + "ranksPerPackage": 1 + } } ] }
-
Amanda Hwang (Code Review) -
EricR Lai (Code Review)
-
Furquan Shaikh (Code Review)
-
Rob Barnes (Code Review)