Change in ...coreboot[master]: southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw
hannah.williams@dell.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32842
Change subject: southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw
outw takes (value, addr) not (addr, value)
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/1
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5..230f6e1 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -40,8 +40,8 @@ /* Disable the watchdog reboot and turn off the watchdog timer */ write8((void *)(DEFAULT_PBASE + PMC_CFG), read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger - outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | - TCO_TMR_HALT); // disable watchdog timer + outw( inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT, + DEFAULT_ABASE + TCO1_CNT); // disable watchdog timer
printk(BIOS_DEBUG, " done.\n");
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32842/1/src/southbridge/intel/fsp_rangeley/e... File src/southbridge/intel/fsp_rangeley/early_init.c:
https://review.coreboot.org/#/c/32842/1/src/southbridge/intel/fsp_rangeley/e... PS1, Line 43: outw( inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT, space prohibited after that open parenthesis '('
Hello Patrick Rudolph, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32842
to look at the new patch set (#2).
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value)
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/2
Hello Patrick Rudolph, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32842
to look at the new patch set (#3).
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value)
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/3
Hello Patrick Rudolph, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32842
to look at the new patch set (#4).
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value)
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams hannah.williams@dell.com --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/4
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 4: Code-Review+1
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 4: Code-Review+2
Hi Hannah. Welcome back!
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 4:
why don't you use read_pmbase16 and write_pmbase16 ? (see src/southbridge/intel/common/pmbase.c )
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 4: Code-Review+1
Hannah W has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 4:
Patch Set 4:
why don't you use read_pmbase16 and write_pmbase16 ? (see src/southbridge/intel/common/pmbase.c )
Yes that can be done. Except the naming was confusing because PMBASE in src/southbridge/intel/common/pmbase.c is actually ACPI base
“ABASE (ACPI_BASE_ADDRESS)—Offset 40h” “PBASE (PMC_BASE_ADDRESS)—Offset 44h”
Hello Patrick Rudolph, HAOUAS Elyes, David Guckian, build bot (Jenkins), Nico Huber, Martin Roth, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32842
to look at the new patch set (#5).
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value) Using write_pmbase16 instead since CONFIG_SOUTHBRIDGE_INTEL_COMMON is enabled
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams hannah.williams@dell.com --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/32842/5/src/southbridge/intel/fsp_rangeley/e... File src/southbridge/intel/fsp_rangeley/early_init.c:
https://review.coreboot.org/#/c/32842/5/src/southbridge/intel/fsp_rangeley/e... PS5, Line 43: write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_TMR_HALT); // disable watchdog timer line over 80 characters
Hello Patrick Rudolph, HAOUAS Elyes, David Guckian, build bot (Jenkins), Nico Huber, Martin Roth, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32842
to look at the new patch set (#6).
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value) Using write_pmbase16 instead since CONFIG_SOUTHBRIDGE_INTEL_COMMON is enabled
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams hannah.williams@dell.com --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/6
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 6: Code-Review+1
HAOUAS Elyes has uploaded a new patch set (#7) to the change originally created by hannah.williams@dell.com. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value) Using write_pmbase16 instead since CONFIG_SOUTHBRIDGE_INTEL_COMMON is enabled
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams hannah.williams@dell.com Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/7
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 7: Code-Review+2
HAOUAS Elyes has uploaded a new patch set (#8) to the change originally created by hannah.williams@dell.com. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value)
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams hannah.williams@dell.com --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/8
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 8: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value)
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams hannah.williams@dell.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32842 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Martin Roth martinroth@google.com --- M src/southbridge/intel/fsp_rangeley/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved HAOUAS Elyes: Looks good to me, approved
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5..cec7a31 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -40,8 +40,8 @@ /* Disable the watchdog reboot and turn off the watchdog timer */ write8((void *)(DEFAULT_PBASE + PMC_CFG), read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger - outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | - TCO_TMR_HALT); // disable watchdog timer + outw(inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT, + DEFAULT_ABASE + TCO1_CNT); // disable watchdog timer
printk(BIOS_DEBUG, " done.\n");
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build bot (Jenkins) (Code Review) -
David Guckian (Code Review)
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Hannah W (Code Review)
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HAOUAS Elyes (Code Review)
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Martin Roth (Code Review)
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Name of user not set (Code Review)