[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra

[Jarried Lin (Code Review)]

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email )

Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
......................................................................

soc/mediatek/mt8196: Add GCE ddren sel control to mminfra

MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction
ACK from WLA: 0x1 or SPM: 0.

In MT8196, this setting should be set to WLA when mminfra power on
every time. Otherwise, GCE will get hang when accessing DRAM.

BUG=b:379039600
TEST=Build pass

Change-Id: I30309b0426f803e28858eb15652a649927f94c7e
Signed-off-by: Jason-jh Lin 
---
M src/soc/mediatek/mt8196/include/soc/mminfra.h
M src/soc/mediatek/mt8196/mminfra.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86027/1

diff --git a/src/soc/mediatek/mt8196/include/soc/mminfra.h b/src/soc/mediatek/mt8196/include/soc/mminfra.h
index 13a4e5c..4404040 100644
--- a/src/soc/mediatek/mt8196/include/soc/mminfra.h
+++ b/src/soc/mediatek/mt8196/include/soc/mminfra.h
@@ -4,6 +4,7 @@
 #define __SOC_MEDIATEK_MMINFRA_H__

/* mminfra_ao */
+#define MMINFRA_GCE_DDREN_SEL		(MMINFRA_AO_CONFIG + 0x418)
 #define MMINFRA_GCE_PROT_EN		(MMINFRA_AO_CONFIG + 0x428)

/* mminfra0 */
diff --git a/src/soc/mediatek/mt8196/mminfra.c b/src/soc/mediatek/mt8196/mminfra.c
index 55ddf47..c5eadf3 100644
--- a/src/soc/mediatek/mt8196/mminfra.c
+++ b/src/soc/mediatek/mt8196/mminfra.c
@@ -26,11 +26,13 @@
    	   GCE_D_SLEEPPORT_RX_EN | GCE_D_HAND_SLEEPPORT_RX_EN |
    	   GCE_D_HAND_SLEEPPORT_TX_EN | GCE_M_SLEEPPORT_RX_EN |
    	   GCE_M_HAND_SLEEPPORT_RX_EN | GCE_M_HAND_SLEEPPORT_TX_EN);
+	write32p(MMINFRA_GCE_DDREN_SEL, 0);
 }

static void mm_gce_release_prot_en(void)
 {
    write32p(MMINFRA_GCE_PROT_EN, 0);
+	write32p(MMINFRA_GCE_DDREN_SEL, 0x1);
 }

static void mm_infra0_lock_prot_en(void)