HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16846
-gerrit
commit 2735669c8edace0122bebfb8802bc68124b4dd6b Author: Elyes HAOUAS ehaouas@noos.fr Date: Sat Oct 1 15:10:11 2016 +0200
mainboard/amd/torpedo: Improve code formatting
Change-Id: I18de4740e0d3512ec81e10b32d13d07a35791b57 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/mainboard/amd/torpedo/BiosCallOuts.c | 264 +++++++++++++++---------------- src/mainboard/amd/torpedo/OemCustomize.c | 196 +++++++++++------------ src/mainboard/amd/torpedo/acpi_tables.c | 57 ++++--- src/mainboard/amd/torpedo/buildOpts.c | 40 ++--- src/mainboard/amd/torpedo/fadt.c | 2 +- src/mainboard/amd/torpedo/gpio.c | 88 +++++------ src/mainboard/amd/torpedo/mainboard.c | 4 +- 7 files changed, 324 insertions(+), 327 deletions(-)
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index b64cef3..cb2e5e5 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -43,147 +43,147 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16;
- FcnData = Data; - MemData = ConfigPtr; + FcnData = Data; + MemData = ConfigPtr;
- Status = AGESA_SUCCESS; - /* Get SB MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8 << 8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- switch(MemData->ParameterListPtr->DDR3Voltage){ - case VOLT1_35: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_25: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_5: - default: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - } - return Status; + switch(MemData->ParameterListPtr->DDR3Voltage){ + case VOLT1_35: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_25: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_5: + default: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + } + return Status; }
/* PCIE slot reset control */ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo;
- UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16;
- FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8 << 8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- if (ResetInfo->ResetControl == DeassertSlotReset) { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); - if (Data8 & BIT7) { - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); - while (!(Data8 & BIT7)) { - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); - } - // GPIO44: PE_GPIO0 MXM Reset - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); - Status = AGESA_SUCCESS; - } - } else { - Status = AGESA_UNSUPPORTED; - } - // Travis - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //DE-Assert ALL PCIE RESET - // APU GPP0 (Dev 4) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); - } else { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported - // GPIO44: PE_GPIO0 MXM Reset - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); - Status = AGESA_SUCCESS; - } - // Travis - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //Assert ALL PCIE RESET - // APU GPP0 (Dev 4) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); - } - return Status; + if (ResetInfo->ResetControl == DeassertSlotReset) { + if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); + if (Data8 & BIT7) { + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); + while (!(Data8 & BIT7)) { + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); + } + // GPIO44: PE_GPIO0 MXM Reset + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); + Status = AGESA_SUCCESS; + } + } else { + Status = AGESA_UNSUPPORTED; + } + // Travis + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); + Data8 |= BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); + //DE-Assert ALL PCIE RESET + // APU GPP0 (Dev 4) + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); + // APU GPP1 (Dev 5) + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); + Data8 |= BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); + // APU GPP2 (Dev 6) + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); + Data8 |= BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); + // APU GPP3 (Dev 7) + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); + Data8 |= BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); + } else { + if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported + // GPIO44: PE_GPIO0 MXM Reset + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); + Data8 &= ~(UINT8)BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); + Status = AGESA_SUCCESS; + } + // Travis + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); + //Assert ALL PCIE RESET + // APU GPP0 (Dev 4) + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); + // APU GPP1 (Dev 5) + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); + Data8 &= ~(UINT8)BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); + // APU GPP2 (Dev 6) + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); + Data8 &= ~(UINT8)BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); + // APU GPP3 (Dev 7) + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); + Data8 &= ~(UINT8)BIT6; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); + } + return Status; } diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 2293039..3c20047 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -23,70 +23,70 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) - }, - // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) - }, - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - } - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) -// { -// DESCRIPTOR_TERMINATE_LIST, -// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), -// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) -// } + // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) + }, + // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) + }, + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + } + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) +// { +// DESCRIPTOR_TERMINATE_LIST, +// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), +// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) +// } };
static const PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) - } + // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) + } };
static const PCIe_COMPLEX_DESCRIPTOR Llano = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] };
/*---------------------------------------------------------------------------------------*/ @@ -107,58 +107,58 @@ static const PCIe_COMPLEX_DESCRIPTOR Llano = {
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) { - AGESA_STATUS Status; - VOID *LlanoPcieComplexListPtr; - VOID *LlanoPciePortPtr; - VOID *LlanoPcieDdiPtr; + AGESA_STATUS Status; + VOID *LlanoPcieComplexListPtr; + VOID *LlanoPciePortPtr; + VOID *LlanoPcieDdiPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams; + ALLOCATE_HEAP_PARAMS AllocHeapParams;
- // GNB PCIe topology Porting + // GNB PCIe topology Porting
- // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList); + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList);
- AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS);
- LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof(Llano); - LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof(Llano); + LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof(PortList); - LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof(PortList); + LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- LibAmdMemFill (LlanoPcieComplexListPtr, - 0, - sizeof(Llano), - &InitEarly->StdHeader); + LibAmdMemFill (LlanoPcieComplexListPtr, + 0, + sizeof(Llano), + &InitEarly->StdHeader);
- LibAmdMemFill (LlanoPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); + LibAmdMemFill (LlanoPciePortPtr, + 0, + sizeof(PortList), + &InitEarly->StdHeader);
- LibAmdMemFill (LlanoPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); + LibAmdMemFill (LlanoPcieDdiPtr, + 0, + sizeof(DdiList), + &InitEarly->StdHeader);
- LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
- ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
- InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; }
@@ -174,9 +174,9 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), - PSO_END + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + PSO_END };
const struct OEM_HOOK OemCustomize = { diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index f014357..fef9156 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -29,33 +29,32 @@ extern u32 apicid_sb900;
unsigned long acpi_fill_madt(unsigned long current) { - - /* create all subtables for processors */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3); - - /* Write SB900 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 2, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 3, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; + /* create all subtables for processors */ + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3); + + /* Write SB900 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 2, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 3, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; } diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index d81748a..656102d 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -96,17 +96,19 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "LlanoPI " - // This string MUST be exactly 8 characters long + // This is the delivery package title, "LlanoPI " + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
-// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common file. + * The values below are based on product and BKDG content, please consult the + * AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -185,18 +187,18 @@ */ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = { - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull }, - { CPU_LIST_TERMINAL } + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull }, + { CPU_LIST_TERMINAL } };
#define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index b20cfc8..56a90a6 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -52,7 +52,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) header->length = 244; header->revision = 1; memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0;
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index ac98557..2287adc 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -40,11 +40,7 @@ #define SB_GPIO_REG27 27 #endif
-void -gpioEarlyInit( - void - ) -{ +void gpioEarlyInit(void) { u8 Flags; u8 Data8 = 0; u8 StripInfo = 0; @@ -57,8 +53,8 @@ gpioEarlyInit( u32 GpioMmioAddr = 0; u32 IoMuxMmioAddr = 0; u32 MiscMmioAddr = 0; - u32 SmiMmioAddr = 0; - u32 andMask32 = 0; + u32 SmiMmioAddr = 0; + u32 andMask32 = 0;
// Enable HUDSON MMIO Base (AcpiMmioAddr) ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); @@ -92,9 +88,9 @@ gpioEarlyInit( Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } // Configure GPIO - if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { - Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); - Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); + if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { + Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); + Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { if ( BoardType == 0 ) { @@ -109,32 +105,32 @@ gpioEarlyInit( andMask32 = ~(1 << (Index - GEVENT_00));
//EventEnable: 0-Disable, 1-Enable - Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); + Mmio32_And_Or(SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
//SciTrig: 0-Falling Edge, 1-Rising Edge - Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); + Mmio32_And_Or(SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
//SciLevl: 0-Edge trigger, 1-Level Trigger - Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); + Mmio32_And_Or(SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
//SmiSciEn: 0-Not send SMI, 1-Send SMI - Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); + Mmio32_And_Or(SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
//SciS0En: 0-Disable, 1-Enable - Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); + Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
//SciMap: 00000b ~ 11111b - RegIndex8=(u8)((Index - GEVENT_00) >> 2); - Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); - Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); + RegIndex8 = (u8)((Index - GEVENT_00) >> 2); + Data8 = (u8)(((Index - GEVENT_00) & 0x3) * 8); + Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
//SmiTrig: 0-Active Low, 1-Active High - Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); + Mmio32_And_Or(SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 - RegIndex8=(u8)((Index - GEVENT_00) >> 4); - Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); - Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); + RegIndex8 = (u8)((Index - GEVENT_00) >> 4); + Data8 = (u8)(((Index - GEVENT_00) & 0xF) * 2); + Mmio32_And_Or(SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); } }
@@ -205,7 +201,7 @@ gpioEarlyInit( Flags = 1; } } - if ( Flags ) + if (Flags) { // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); @@ -228,7 +224,7 @@ gpioEarlyInit( ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); } // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + //RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); } else { @@ -394,11 +390,11 @@ gpioEarlyInit( // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { // disable Onboard NEC USB3.0 controller if (!CONFIG_ONBOARD_USB30) { - RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 - RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE } // }
@@ -407,41 +403,41 @@ gpioEarlyInit( // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE // GPIO07: BT_ON, 0 - OFF, 1 - ON // -if (!CONFIG_ONBOARD_BLUETOOTH) { -//- if (SystemConfiguration.amdBlueTooth == 1) { + if (!CONFIG_ONBOARD_BLUETOOTH) { + //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); -//- } -} + //- } + }
// // WebCam control: // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF // -if (!CONFIG_ONBOARD_WEBCAM) { -//- if (SystemConfiguration.amdWebCam == 1) { + if (!CONFIG_ONBOARD_WEBCAM) { + //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); -//- } -} + //- } + }
// // Travis enable: // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE // -if (!CONFIG_ONBOARD_TRAVIS) { -//- if (SystemConfiguration.amdTravisCtrl == 0) { + if (!CONFIG_ONBOARD_TRAVIS) { + //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); -//- } -} + //- } + }
// // Disable Light Sensor if needed // -if (CONFIG_ONBOARD_LIGHTSENSOR) { -//- if (SystemConfiguration.amdLightSensor == 1) { - RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); -//- } -} + if (CONFIG_ONBOARD_LIGHTSENSOR) { + //- if (SystemConfiguration.amdLightSensor == 1) { + RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); + //- } + }
} diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index d90cb84..86339ef 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -49,9 +49,9 @@ void set_pcie_dereset(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); }
struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable, };
-
HAOUAS Elyes