Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
Hannah Williams has uploaded a new change for review. ( https://review.coreboot.org/19759 )
Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio ......................................................................
soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio
Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams hannah.williams@intel.com --- A src/soc/intel/common/block/gpio/Kconfig A src/soc/intel/common/block/gpio/Makefile.inc A src/soc/intel/common/block/gpio/gpio.c A src/soc/intel/common/block/include/intelblocks/gpio.h A src/soc/intel/common/block/include/intelblocks/gpio_defs.h 5 files changed, 802 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/19759/1
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig new file mode 100644 index 0000000..1f8412c --- /dev/null +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -0,0 +1,18 @@ +config SOC_INTEL_COMMON_BLOCK_GPIO + bool + help + Intel Processor common GPIO support + +config DEBUG_SOC_COMMON_BLOCK_GPIO + depends on SOC_INTEL_COMMON_BLOCK_GPIO + bool "Output verbose GPIO debug messages" + default n + help + This option enables GPIO debug messages + +config GPIO_NUM_PAD_CFG_REGS + depends on SOC_INTEL_COMMON_BLOCK_GPIO + int "Number of Pad Config Registers DW0, DW1, etc" + default 2 + help + This option specifies the number of DWx registers for each pad diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc new file mode 100644 index 0000000..bf40397 --- /dev/null +++ b/src/soc/intel/common/block/gpio/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c new file mode 100644 index 0000000..e06ac67 --- /dev/null +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -0,0 +1,342 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <assert.h> +#include <gpio.h> +#include <intelblocks/pcr.h> +#include <soc/gpio.h> +#include <soc/pcr_ids.h> +#include <soc/pm.h> +#include <types.h> + +const struct pad_community *gpio_get_community(gpio_t pad) +{ + size_t gpio_communities; + size_t i; + const struct pad_community *comm; + comm = soc_gpio_get_community(&gpio_communities); + for (i = 0; i < gpio_communities; i++, comm++) { + if (pad >= comm->first_pad && pad <= comm->last_pad) + return comm; + } + printk(BIOS_ERR, "%s pad %d not found\n", __func__, pad); + return NULL; +} + +static void gpio_configure_owner(const struct pad_config *cfg, + uint16_t port, int pin) +{ + uint16_t hostsw_reg; + + /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad + * needs GPIO driver ownership. + */ + if (!(cfg->pad_config1 & PAD_CFG1_GPIO_DRIVER)) + return; + + /* Based on the gpio pin number configure the corresponding bit in + * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. + */ + hostsw_reg = HOSTSW_OWN_REG_0 + ((pin / 32) * sizeof(uint32_t)); + pcr_or32(port, hostsw_reg, (1 << (pin % 32))); +} + +static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin) +{ + uint32_t value; + uint16_t sts_reg; + uint16_t en_reg; + int group; + + if (((cfg->pad_config0) & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI) + return; + + group = pin / GPIO_MAX_NUM_PER_GROUP; + + sts_reg = GPI_SMI_STS_OFFSET(group); + value = pcr_read32(port, sts_reg); + /* Write back 1 to reset the sts bits */ + pcr_write32(port, sts_reg, value); + + /* Set enable bits */ + en_reg = GPI_SMI_EN_OFFSET(group); + pcr_or32(port, en_reg, (1 << (pin % GPIO_MAX_NUM_PER_GROUP))); +} + +__attribute__((weak)) void soc_gpio_configure_itss( + const struct pad_config *cfg, + uint16_t port, gpio_t pad_cfg_offset) +{ +} + +/* Number of DWx config registers can be different for different SOCs */ +static uint16_t soc_gpio_get_pad_config_offset( + const struct pad_community *comm, gpio_t pad) +{ + return PAD_CFG_BASE + ((pad) * + GPIO_DWx_SIZE(CONFIG_GPIO_NUM_PAD_CFG_REGS)); +} + +static void gpio_configure_pad(const struct pad_config *cfg) +{ + const struct pad_community *comm = gpio_get_community(cfg->pad); + uint16_t config_offset; + uint32_t pad_conf0; + uint32_t pad_conf1; + + config_offset = soc_gpio_get_pad_config_offset(comm, + cfg->pad - comm->first_pad); + pad_conf0 = pcr_read32(comm->port, config_offset); + pad_conf1 = pcr_read32(comm->port, config_offset); + if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) + printk(BIOS_DEBUG, + "gpio_padcfg [0x%02x, %d] DW0 [0x%08x : 0x%08x] " + "DW1 [0x%08x : 0x%08x]\n", + comm->port, + (cfg->pad - comm->first_pad), + pad_conf0,/* old value */ + cfg->pad_config0, /* new value */ + pad_conf1,/* old value */ + cfg->pad_config1); /* new value */ + + pad_conf0 &= ~PAD_DW0_MASK; + pcr_write32(comm->port, config_offset, pad_conf0 | + (cfg->pad_config0 & PAD_DW0_MASK)); + pad_conf1 &= ~PAD_DW1_MASK; + pcr_write32(comm->port, config_offset + GPIO_DWx_SIZE(1), + pad_conf1 | + (cfg->pad_config1 & PAD_DW1_MASK)); + + soc_gpio_configure_itss(cfg, comm->port, config_offset); + gpio_configure_owner(cfg, comm->port, cfg->pad - comm->first_pad); + + gpi_enable_smi(cfg, comm->port, cfg->pad - comm->first_pad); +} + +void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) +{ + uint32_t i; + + for (i = 0; i < num_pads; i++) + gpio_configure_pad(cfg + i); +} + +void *gpio_dwx_address(const gpio_t pad) +{ + /* Calculate Address of DW0 register for given GPIO + * pad - GPIO number + * returns - address of GPIO + */ + const struct pad_community *comm = gpio_get_community(pad); + uint16_t config_offset; + + config_offset = soc_gpio_get_pad_config_offset(comm, + pad - comm->first_pad); + return pcr_reg_address(comm->port, config_offset); +} + +uint8_t gpio_get_pad_portid(const gpio_t pad) +{ + /* Get the port id of given pad + * pad - GPIO number + * returns - given pad port id + */ + const struct pad_community *comm = gpio_get_community(pad); + return comm->port; +} + +void gpio_input_pulldown(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_input_pullup(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, UP_20K, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_input(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_output(gpio_t gpio, int value) +{ + struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP); + gpio_configure_pad(&cfg); +} + +int gpio_get(gpio_t gpio_num) +{ + const struct pad_community *comm = gpio_get_community(gpio_num); + uint16_t config_offset; + uint32_t reg; + + config_offset = soc_gpio_get_pad_config_offset(comm, + gpio_num - comm->first_pad); + reg = pcr_read32(comm->port, config_offset); + + return !!(reg & PAD_CFG0_RX_STATE); +} + +void gpio_set(gpio_t gpio_num, int value) +{ + const struct pad_community *comm = gpio_get_community(gpio_num); + uint16_t config_offset; + + config_offset = soc_gpio_get_pad_config_offset(comm, + gpio_num - comm->first_pad); + pcr_rmw32(comm->port, config_offset, + ~PAD_CFG0_TX_STATE, (!!value & PAD_CFG0_TX_STATE)); +} + +uint16_t gpio_acpi_pin(gpio_t gpio_num) +{ + const struct pad_community *comm = + gpio_get_community(gpio_num); + + return (gpio_num - comm->first_pad); +} + +static void print_gpi_status(const struct gpi_status *sts) +{ + int i; + int group; + int index = 0; + int bit_set; + int num_groups; + int abs_bit; + size_t gpio_communities; + const struct pad_community *comm; + + comm = soc_gpio_get_community(&gpio_communities); + for (i = 0; i < gpio_communities; i++) { + num_groups = comm->num_gpi_regs; + index = comm->gpi_offset; + for (group = 0; group < num_groups; group++, index++) { + for (bit_set = 31; bit_set >= 0; bit_set--) { + if (!(sts->grp[index] & (1 << bit_set))) + continue; + + abs_bit = bit_set; + abs_bit += group * GPIO_MAX_NUM_PER_GROUP; + printk(BIOS_DEBUG, "%s %d\n", comm->name, + abs_bit); + } + } + comm++; + } +} + +void gpi_clear_get_smi_status(struct gpi_status *sts) +{ + int i; + int group; + int index = 0; + uint32_t sts_value; + uint32_t en_value; + size_t gpio_communities; + int num_groups; + const struct pad_community *comm; + + comm = soc_gpio_get_community(&gpio_communities); + for (i = 0; i < gpio_communities; i++) { + num_groups = comm->num_gpi_regs; + index = comm->gpi_offset; + for (group = 0; group < num_groups; group++, index++) { + sts_value = pcr_read32(comm->port, + GPI_SMI_STS_OFFSET(group)); + en_value = pcr_read32(comm->port, + GPI_SMI_EN_OFFSET(group)); + sts->grp[index] = sts_value & en_value; + /* Clear the set status bits. */ + pcr_write32(comm->port, + GPI_SMI_STS_OFFSET(group), sts->grp[index]); + } + comm++; + } + + if (IS_ENABLED(CONFIG_DEBUG_SMI)) + print_gpi_status(sts); + +} + +int gpi_status_get(const struct gpi_status *sts, gpio_t pad) +{ + uint8_t sts_index; + const struct pad_community *comm = gpio_get_community(pad); + + sts_index = comm->gpi_offset + ((pad - comm->first_pad) / + GPIO_MAX_NUM_PER_GROUP); + + return !!(sts->grp[sts_index] & (1 << + ((pad - comm->first_pad) % GPIO_MAX_NUM_PER_GROUP))); +} + +/* Helper function to map PMC register groups to tier1 sci groups */ +__attribute__((weak)) int soc_gpe_route_to_gpio(int route) +{ + return route; +} + +void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d) +{ + int i; + uint32_t misccfg_mask; + uint32_t misccfg_value; + int ret; + size_t gpio_communities; + const struct pad_community *comm; + + /* Get the group here for community specific MISCCFG register. + * If any of these returns -1 then there is some error in devicetree + * where the group is probably hardcoded and does not comply with the + * PMC group defines. So we return from here and MISCFG is set to + * default. + */ + ret = soc_gpe_route_to_gpio(gpe0b); + if (ret == -1) + return; + gpe0b = ret; + + ret = soc_gpe_route_to_gpio(gpe0c); + if (ret == -1) + return; + gpe0c = ret; + + ret = soc_gpe_route_to_gpio(gpe0d); + if (ret == -1) + return; + gpe0d = ret; + + misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT; + misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; + misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT; + + /* Program GPIO_MISCCFG */ + misccfg_mask = ~(MISCCFG_GPE0_DW2_MASK | + MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK); + + comm = soc_gpio_get_community(&gpio_communities); + for (i = 0; i < gpio_communities; i++, comm++) { + + pcr_rmw32(comm->port, GPIO_MISCCFG, + misccfg_mask, misccfg_value); + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h new file mode 100644 index 0000000..085cf64 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_INTELBLOCKS_GPIO_H_ +#define _SOC_INTELBLOCKS_GPIO_H_ + +#ifndef __ACPI__ +#include <types.h> +#endif +#include <soc/gpio.h> +#include "gpio_defs.h" + +#ifndef __ACPI__ +typedef uint32_t gpio_t; + +#define GPIO_DWx_SIZE(x) (sizeof(uint32_t) * (x)) + +struct pad_config { + int pad;/* offset of pad within community */ + uint32_t pad_config0; + uint32_t pad_config1; +}; + +struct pad_community { + gpio_t first_pad; /* first pad in community */ + gpio_t last_pad; /* last pad in community */ + uint8_t port; + size_t num_gpi_regs;/* number of gpi registers in community */ + uint8_t gpi_offset; /* specifies offset in struct gpi_status */ + const char *name; +}; + +/* + * Structure to represent GPI status for GPE and SMI. Use helper + * functions for interrogating particular GPIs. + */ +struct gpi_status; + + +/* + * Returns GPIO community map for specified pad + */ +const struct pad_community *gpio_get_community(gpio_t pad); + +/* + * Returns the first community in the list. This will help to iterate + * through the list. It also returns total number of pad communities + */ +const struct pad_community *soc_gpio_get_community(size_t + *num_communities); + +/* + * Clear GPI SMI status and fill in the structure representing enabled + * and set status. + */ +void gpi_clear_get_smi_status(struct gpi_status *sts); + +/* Return 1 if gpio is set in the sts. Otherwise 0. */ +int gpi_status_get(const struct gpi_status *sts, gpio_t gpi); + +/* + * Configuration for raw pads. Some pads are designated as only special function + * pins, and don't have an associated GPIO number, so we need to expose the raw + * pad configuration functionality. + */ +void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); + +/* + * Calculate Address of DW0 register for given GPIO + */ +void * gpio_dwx_address(const gpio_t pad); + +/* + * Returns the gpio group number + */ +int soc_gpe_route_to_gpio(int route); + +/* + * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG + * are passed which is then mapped to proper groups for MISCCFG. This basically + * sets the MISCCFG register bits: + * dw0 = gpe0_route[11:8]. This is ACPI GPE0b. + * dw1 = gpe0_route[15:12]. This is ACPI GPE0c. + * dw2 = gpe0_route[19:16]. This is ACPI GPE0d. + */ +void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d); + +/* + * Handle any ITSS specific configuration + */ +void soc_gpio_configure_itss(const struct pad_config *cfg, + uint16_t port, gpio_t pad_cfg_offset); + +/* + * Function provides read access to the GPIO config space registers + */ +uint32_t gpio_config_read(const struct pad_community *comm, uint16_t reg_offset); + +/* + * Function provides read access to the GPIO config space registers + */ +void gpio_config_write(const struct pad_community *comm, uint16_t reg_offset, + uint32_t value); + +/* + * Function returns PCR port ID for this pad + */ +uint8_t gpio_get_pad_portid(const gpio_t pad); + +#endif +#endif /* _SOC_INTELBLOCKS_GPIO_H_ */ + diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h new file mode 100644 index 0000000..a81d905 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -0,0 +1,313 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BLOCK_GPIO_DEFS_H_ +#define _SOC_BLOCK_GPIO_DEFS_H_ + +#define LO 0 +#define HI 1 + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) + +#define PAD_CFG0_TX_STATE (1 << 0) +#define PAD_CFG0_RX_STATE_BIT 1 +#define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT) +#define PAD_CFG0_TX_DISABLE (1 << 8) +#define PAD_CFG0_RX_DISABLE (1 << 9) +#define PAD_CFG0_MODE_MASK (7 << 10) +#define PAD_CFG0_MODE_GPIO (0 << 10) +#define PAD_CFG0_MODE_FUNC(x) ((x) << 10) +#define PAD_CFG0_MODE_NF1 (1 << 10) +#define PAD_CFG0_MODE_NF2 (2 << 10) +#define PAD_CFG0_MODE_NF3 (3 << 10) +#define PAD_CFG0_MODE_NF4 (4 << 10) +#define PAD_CFG0_MODE_NF5 (5 << 10) +#define PAD_CFG0_MODE_NF6 (6 << 10) +#define PAD_CFG0_ROUTE_MASK (0xF << 17) +#define PAD_CFG0_ROUTE_NMI (1 << 17) +#define PAD_CFG0_ROUTE_SMI (1 << 18) +#define PAD_CFG0_ROUTE_SCI (1 << 19) +#define PAD_CFG0_ROUTE_IOAPIC (1 << 20) +#define PAD_CFG0_RXTENCFG_MASK (3 << 21) +#define PAD_CFG0_RXINV_MASK (1 << 23) +#define PAD_CFG0_RX_POL_INVERT (1 << 23) +#define PAD_CFG0_RX_POL_NONE (0 << 23) +#define PAD_CFG0_PREGFRXSEL (1 << 24) +#define PAD_CFG0_TRIG_MASK (3 << 25) +#define PAD_CFG0_TRIG_LEVEL (0 << 25) +#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ +#define PAD_CFG0_TRIG_OFF (2 << 25) +#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) +#define PAD_CFG0_RXRAW1_MASK (1 << 28) +#define PAD_CFG0_RXPADSTSEL_MASK (1 << 29) +#define PAD_CFG0_RESET_MASK (3 << 30) +#define PAD_CFG0_RESET_PWROK (0 << 30) +#define PAD_CFG0_RESET_DEEP (1 << 30) +#define PAD_CFG0_RESET_PLTRST (2 << 30) +#define PAD_CFG0_RESET_RSMRST (3 << 30) + +/* Use the fourth bit in IntSel field to indicate gpio + * ownership. This field is RO and hence not used during + * gpio configuration. + */ +#define PAD_CFG1_GPIO_DRIVER (0x1 << 4) +#define PAD_CFG1_IRQ_MASK (0xff << 0) +#define PAD_CFG1_IOSTERM_MASK (0x3 << 8) +#define PAD_CFG1_IOSTERM_SAME (0x0 << 8) +#define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8) +#define PAD_CFG1_IOSTERM_ENPD (0x2 << 8) +#define PAD_CFG1_IOSTERM_ENPU (0x3 << 8) +#define PAD_CFG1_PULL_MASK (0xf << 10) +#define PAD_CFG1_PULL_NONE (0x0 << 10) +#define PAD_CFG1_PULL_DN_5K (0x2 << 10) +#define PAD_CFG1_PULL_DN_20K (0x4 << 10) +#define PAD_CFG1_PULL_UP_1K (0x9 << 10) +#define PAD_CFG1_PULL_UP_5K (0xa << 10) +#define PAD_CFG1_PULL_UP_2K (0xb << 10) +#define PAD_CFG1_PULL_UP_20K (0xc << 10) +#define PAD_CFG1_PULL_UP_667 (0xd << 10) +#define PAD_CFG1_PULL_NATIVE (0xf << 10) +/* Tx enabled driving last value driven, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 14) +/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller + * internally */ +#define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 14) +/* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller + * internally */ +#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1 (0x2 << 14) +/* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller + * internally */ +#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0 (0x3 << 14) +/* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller + * internally */ +#define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 14) +/* Tx enabled driving 0, Rx enabled */ +#define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 14) +/* Tx enabled driving 1, Rx enabled */ +#define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 14) +/* Hi-Z, Rx driving 0 back to its controller internally */ +#define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 14) +/* Hi-Z, Rx driving 1 back to its controller internally */ +#define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 14) +#define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 14) /* Tx disabled, Rx enabled */ +#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */ +#define PAD_CFG1_IOSSTATE_MASK (0xf << 14) /* mask to extract Iostandby bits */ +#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ +/* voltage tolerance 0=3.3V default 1=1.8V tolerant */ +#define PAD_CFG1_TOL_MASK (0x1 << 25) +#define PAD_CFG1_TOL_1V8 (0x1 << 25) + +#define PAD_FUNC(value) PAD_CFG0_MODE_##value +#define PAD_RESET(value) PAD_CFG0_RESET_##value +#define PAD_PULL(value) PAD_CFG1_PULL_##value +#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value +#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value +#define PAD_IRQ_CFG(route, trig, inv) \ + (PAD_CFG0_ROUTE_##route | \ + PAD_CFG0_TRIG_##trig | \ + (PAD_CFG0_RX_POL_##inv)) + +#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ + { \ + .pad = __pad, \ + .pad_config0 = __config0, \ + .pad_config1 = __config1, \ + } + +/* Native function configuration */ +#define PAD_CFG_NF(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +/* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. */ +#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ + PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) + +/* Native function configuration for standby state */ +#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate)) + +/* Native function configuration for standby state, also configuring + iostandby as masked */ +#define PAD_CFG_NF_NOIOS(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(IGNORE)) + +/* Native function configuration for standby state, also configuring + iosstate and iosterm */ +#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_NF_IOS PAD_CFG_NF_IOSSTATE_IOSTERM + +/* Native function configuration for standby state, also configuring + 1iosstate as HIZCRx1 and iosterm as DISPUPD */ +#define PAD_CFG_NF_IOS_1(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)) + +/* Native function configuration for standby state, also configuring + iosstate as HIZCRx1 and iosterm as ENPU */ +#define PAD_CFG_NF_IOS_2(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)) + +/* Native function configuration for standby state, also configuring + iosstate as HIZCRx1 and iosterm as DISPUPD */ +#define PAD_CFG_NF_IOS_3(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)) + +/* General purpose output, no pullup/down. */ +#define PAD_CFG_GPO(pad, val, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose output, no pullup/down. */ +#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) + +/* General purpose output. */ +#define PAD_CFG_GPO_1(pad, val, rst, pull, iosstate, ioterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) + +/* General purpose input */ +#define PAD_CFG_GPI(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose input. The following macro sets the + * Host Software Pad Ownership to GPIO Driver mode. + */ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE)) + +#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_RX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* No Connect configuration for unused pad. + * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term + */ +#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) + +/* General purpose input, routed to APIC */ +#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose input, routed to APIC - with IOStandby Config*/ +#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* General purpose input, routed to APIC - with IOStandby Config and + GPIO DRIVER config*/ +#define PAD_CFG_GPI_APIC_GPIO_DRIVER(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm) | \ + PAD_CFG1_GPIO_DRIVER) + +/* + * The following APIC macros assume the APIC will handle the filtering + * on its own end. One just needs to pass an active high message into the + * ITSS. + */ +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) + +#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) + +/* General purpose input, routed to SMI */ +#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose input, routed to SMI */ +#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) + +#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ + PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) + +/* General purpose input, routed to SCI */ +#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose input, routed to SCI */ +#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) + +#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ + PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) + +/* General purpose input, routed to NMI */ +#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +#endif /* _SOC_BLOCK_GPIO_DEFS_H_ */
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Hannah Williams (Code Review)