Change in coreboot[master]: intel/{ironlake,sandybridge}/gma.c: Use <drivers/intel/gma/i915_reg.h...
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61648 )
Change subject: intel/{ironlake,sandybridge}/gma.c: Use <drivers/intel/gma/i915_reg.h> macros ......................................................................
intel/{ironlake,sandybridge}/gma.c: Use <drivers/intel/gma/i915_reg.h> macros
Change-Id: If4c273477a1e4f50dcfc033611b90cd07a3c2542 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/sandybridge/gma.c 2 files changed, 78 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/61648/1
diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index a0325d1..37abd89 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -10,6 +10,7 @@ #include <device/pci_ops.h> #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/intel_bios.h> #include <drivers/intel/gma/libgfxinit.h> #include <pc80/vga.h> @@ -70,47 +71,47 @@ printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
/* Setup Digital Port Hotplug */ - reg32 = gtt_read(0xc4030); + reg32 = gtt_read(PCH_PORT_HOTPLUG); if (!reg32) { reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; - gtt_write(0xc4030, reg32); + gtt_write(PCH_PORT_HOTPLUG, reg32); }
/* Setup Panel Power On Delays */ - reg32 = gtt_read(0xc7208); + reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); - gtt_write(0xc7208, reg32); + gtt_write(PCH_PP_ON_DELAYS, reg32); }
/* Setup Panel Power Off Delays */ - reg32 = gtt_read(0xc720c); + reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); - gtt_write(0xc720c, reg32); + gtt_write(PCH_PP_OFF_DELAYS, reg32); }
/* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { - reg32 = gtt_read(0xc7210); + reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0xff; reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; - gtt_write(0xc7210, reg32); + gtt_write(PCH_PP_DIVISOR, reg32); }
/* Enable Backlight if needed */ if (conf->gpu_cpu_backlight) { - gtt_write(0x48250, (1 << 31)); - gtt_write(0x48254, conf->gpu_cpu_backlight); + gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); + gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); } if (conf->gpu_pch_backlight) { - gtt_write(0xc8250, (1 << 31)); - gtt_write(0xc8254, conf->gpu_pch_backlight); + gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); + gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); } }
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 9d01533..9b67a1d 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -10,6 +10,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -314,19 +315,19 @@
if (is_sandy || cpu_stepping() < IVB_STEP_C0) { /* 1: Enable force wake */ - gtt_write(0xa18c, 0x00000001); - gtt_poll(0x130090, (1 << 0), (1 << 0)); + gtt_write(FORCEWAKE, 0x00000001); + gtt_poll(FORCEWAKE_ACK, (1 << 0), (1 << 0)); } else { - gtt_write(0xa180, 1 << 5); - gtt_write(0xa188, 0xffff0001); - gtt_poll(0x130040, (1 << 0), (1 << 0)); + gtt_write(ECOBUS, FORCEWAKE_MT_ENABLE); + gtt_write(FORCEWAKE_MT, 0xffff0001); + gtt_poll(FORCEWAKE_MT_ACK, (1 << 0), (1 << 0)); }
if (is_sandy) { /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ - reg32 = gtt_read(0x42004); + reg32 = gtt_read(ILK_DISPLAY_CHICKEN2); reg32 |= (1 << 14) | (1 << 15); - gtt_write(0x42004, reg32); + gtt_write(ILK_DISPLAY_CHICKEN2, reg32); }
if (!is_sandy) { @@ -384,54 +385,54 @@ gtt_write(0xa080, 0x00000004);
/* 6: ECO bits */ - reg32 = gtt_read(0xa180); + reg32 = gtt_read(ECOBUS); reg32 |= (1 << 26) | (1 << 31); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) reg32 |= (1 << 20); - gtt_write(0xa180, reg32); + gtt_write(ECOBUS, reg32);
/* 6a: for SnB step D2+ only */ if (is_sandy && cpu_stepping() >= SNB_STEP_D2) { - reg32 = gtt_read(0x9400); - reg32 |= (1 << 7); - gtt_write(0x9400, reg32); + reg32 = gtt_read(GEN6_UCGCTL1); + reg32 |= GEN6_CSUNIT_CLOCK_GATE_DISABLE; + gtt_write(GEN6_UCGCTL1, reg32);
- reg32 = gtt_read(0x941c); + reg32 = gtt_read(GEN6_GDRST); reg32 &= 0xf; - reg32 |= (1 << 1); - gtt_write(0x941c, reg32); - gtt_poll(0x941c, (1 << 1), (0 << 1)); + reg32 |= GEN6_GRDOM_RENDER; + gtt_write(GEN6_GDRST, reg32); + gtt_poll(GEN6_GDRST, (1 << 1), (0 << 1)); }
if (is_sandy) { /* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000000); + gtt_write(GEN7_MISCCPCTL, 0x00000000); } else { reg32 = gtt_read(0x907c); reg32 |= (1 << 16); gtt_write(0x907c, reg32);
/* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000001); + gtt_write(GEN7_MISCCPCTL, 0x00000001); }
/* 7 */ - if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { - gtt_write(0x138128, 0x00000029); /* Mailbox Data */ - gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ - if (gtt_poll(0x138124, (1 << 31), (0 << 31))) - gtt_write(0x138124, 0x8000000a); - gtt_poll(0x138124, (1 << 31), (0 << 31)); + if (gtt_poll(GEN6_PCODE_MAILBOX, (1 << 31), (0 << 31))) { + gtt_write(GEN6_PCODE_DATA, 0x00000029); /* Mailbox Data */ + gtt_write(GEN6_PCODE_MAILBOX, 0x80000004); /* Mailbox Cmd for RC6 VID */ + if (gtt_poll(GEN6_PCODE_MAILBOX, (1 << 31), (0 << 31))) + gtt_write(GEN6_PCODE_MAILBOX, 0x8000000a); + gtt_poll(GEN6_PCODE_MAILBOX, (1 << 31), (0 << 31)); }
/* 8 */ - gtt_write(0xa090, 0x00000000); /* RC Control */ - gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ - gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ - gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ - gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ - gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ + gtt_write(GEN6_RC_CONTROL, 0x00000000); /* RC Control */ + gtt_write(GEN6_RC1_WAKE_RATE_LIMIT, 0x03e80000); /* RC1e Wake Rate Limit */ + gtt_write(GEN6_RC6_WAKE_RATE_LIMIT, 0x0028001e); /* RC6/6p Wake Rate Limit */ + gtt_write(GEN6_RC6pp_WAKE_RATE_LIMIT, 0x0000001e); /* RC6pp Wake Rate Limit */ + gtt_write(GEN6_RC_EVALUATION_INTERVAL, 0x0001e848); /* RC Evaluation Interval */ + gtt_write(GEN6_RC_IDLE_HYSTERSIS, 0x00000019); /* RC Idle Hysteresis */
/* 9 */ gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ @@ -439,20 +440,20 @@ gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */
/* 10 */ - gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ - gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ - gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ - gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ - gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ + gtt_write(GEN6_RC_SLEEP, 0x00000000); /* Unblock Ack to Busy */ + gtt_write(GEN6_RC1e_THRESHOLD, 0x000003e8); /* RC1e Threshold */ + gtt_write(GEN6_RC6_THRESHOLD, 0x0000c350); /* RC6 Threshold */ + gtt_write(GEN6_RC6p_THRESHOLD, 0x000186a0); /* RC6p Threshold */ + gtt_write(GEN6_RC6pp_THRESHOLD, 0x0000fa00); /* RC6pp Threshold */
/* 11 */ - gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ - gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ - gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ - gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ - gtt_write(0xa068, 0x000186a0); /* RP Up EI */ - gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ - gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ + gtt_write(GEN6_RP_DOWN_TIMEOUT, 0x000f4240); /* RP Down Timeout */ + gtt_write(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); /* RP Interrupt Limits */ + gtt_write(GEN6_RP_UP_THRESHOLD, 0x00015f90); /* RP Up Threshold */ + gtt_write(GEN6_RP_DOWN_THRESHOLD, 0x000186a0); /* RP Down Threshold */ + gtt_write(GEN6_RP_UP_EI, 0x000186a0); /* RP Up EI */ + gtt_write(GEN6_RP_DOWN_EI, 0x000493e0); /* RP Down EI */ + gtt_write(GEN6_RP_IDLE_HYSTERSIS, 0x0000000a); /* RP Idle Hysteresis */
/* * 11a: Enable Render Standby (RC6) @@ -462,7 +463,7 @@ * Unfortunately it does not work reliably on all SKUs so * disable it here and it can be enabled by the kernel. */ - gtt_write(0xa090, 0x88040000); /* HW RC Control */ + gtt_write(GEN6_RC_CONTROL, 0x88040000); /* HW RC Control */
/* 12: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ @@ -471,13 +472,13 @@ reg32 >>= 16; reg32 &= 0x7f; reg32 <<= 25; - gtt_write(0xa008, reg32); + gtt_write(GEN6_RPNSWREQ, reg32);
/* 13: RP Control */ - gtt_write(0xa024, 0x00000592); + gtt_write(GEN6_RP_CONTROL, 0x00000592);
/* 14: Enable PM Interrupts */ - gtt_write(0x4402c, 0x03000076); + gtt_write(GEN6_PMIER, 0x03000076);
/* Clear 0x6c024 [8:6] */ reg32 = gtt_read(0x6c024); @@ -506,59 +507,59 @@
/* 15: Deassert Force Wake */ if (is_sandybridge() || cpu_stepping() < IVB_STEP_C0) { - gtt_write(0xa18c, gtt_read(0xa18c) & ~1); - gtt_poll(0x130090, (1 << 0), (0 << 0)); + gtt_write(FORCEWAKE, gtt_read(FORCEWAKE) & ~1); + gtt_poll(FORCEWAKE_ACK, (1 << 0), (0 << 0)); } else { - gtt_write(0xa188, 0x1fffe); - if (gtt_poll(0x130040, (1 << 0), (0 << 0))) - gtt_write(0xa188, gtt_read(0xa188) | 1); + gtt_write(FORCEWAKE_MT, 0x1fffe); + if (gtt_poll(FORCEWAKE_MT_ACK, (1 << 0), (0 << 0))) + gtt_write(FORCEWAKE_MT, gtt_read(FORCEWAKE_MT) | 1); }
/* 16: SW RC Control */ - gtt_write(0xa094, 0x00060000); + gtt_write(GEN6_RC_STATE, 0x00060000);
/* Setup Digital Port Hotplug */ - reg32 = gtt_read(0xc4030); + reg32 = gtt_read(PCH_PORT_HOTPLUG); if (!reg32) { reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; - gtt_write(0xc4030, reg32); + gtt_write(PCH_PORT_HOTPLUG, reg32); }
/* Setup Panel Power On Delays */ - reg32 = gtt_read(0xc7208); + reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); - gtt_write(0xc7208, reg32); + gtt_write(PCH_PP_ON_DELAYS, reg32); }
/* Setup Panel Power Off Delays */ - reg32 = gtt_read(0xc720c); + reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); - gtt_write(0xc720c, reg32); + gtt_write(PCH_PP_OFF_DELAYS, reg32); }
/* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { - reg32 = gtt_read(0xc7210); + reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0xff; reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; - gtt_write(0xc7210, reg32); + gtt_write(PCH_PP_DIVISOR, reg32); }
/* Enable Backlight if needed */ if (conf->gpu_cpu_backlight) { - gtt_write(0x48250, (1 << 31)); - gtt_write(0x48254, conf->gpu_cpu_backlight); + gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); + gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); } if (conf->gpu_pch_backlight) { - gtt_write(0xc8250, (1 << 31)); - gtt_write(0xc8254, conf->gpu_pch_backlight); + gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); + gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); } }
-
HAOUAS Elyes (Code Review)