Change in coreboot[master]: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59929 )

Change subject: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
......................................................................

soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume

According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware...
> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit (and thus passing control to OSPM). For ACPI only
> platforms (where SCI_EN is always set), when transitioning from either
> the mechanical off (G3) or soft-off state to the G0 working state this
> register is cleared prior to entering the G0 working state.

This means we don't want to clear the PM1 register on resume. By
clearing it the linux kernel can't correctly increment the wake count
when the power button is pressed. The AMD platforms implement the _SWS
ACPI methods, but the linux kernel doesn't actually use these methods.

BUG=b:172021431
TEST=suspend zork and push power button and verify power button wake_count
increments. Verified other wake sources still work.

Signed-off-by: Raul E Rangel 
Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561
---
M src/soc/amd/cezanne/fch.c
M src/soc/amd/common/block/cpu/smm/finalize.c
M src/soc/amd/picasso/fch.c
M src/soc/amd/stoneyridge/romstage.c
4 files changed, 2 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59929/1

diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index dd19c31..8cd1212 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -199,7 +199,6 @@

acpi_pm_gpe_add_events_print_events();
    gpio_add_events();
-	acpi_clear_pm_gpe_status();

gpp_clk_setup();
    fch_clk_output_48Mhz();
diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c
index ec975be..73b2121 100644
--- a/src/soc/amd/common/block/cpu/smm/finalize.c
+++ b/src/soc/amd/common/block/cpu/smm/finalize.c
@@ -41,6 +41,8 @@
    finalize_cores();

if (!acpi_is_wakeup_s3()) {
+		acpi_clear_pm_gpe_status();
+
    	if (CONFIG(HAVE_SMI_HANDLER))
    		acpi_disable_sci();
    	else
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c
index 44acc81..03ba914 100644
--- a/src/soc/amd/picasso/fch.c
+++ b/src/soc/amd/picasso/fch.c
@@ -225,8 +225,6 @@
    acpi_pm_gpe_add_events_print_events();
    gpio_add_events();

-	acpi_clear_pm_gpe_status();
-
    al2ahb_clock_gate();

gpp_clk_setup();
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index e316d21..c732f75 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -214,6 +214,5 @@
    	acpi_fill_pm_gpe_state(&state->gpe_state);
    	acpi_pm_gpe_add_events_print_events();
    }
-	acpi_clear_pm_gpe_status();
 }
 ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)