Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39700 )
Change subject: nb/amd/pi/00730F01: initialize GNB IOAPIC ......................................................................
nb/amd/pi/00730F01: initialize GNB IOAPIC
Northbridge IOAPIC was not being initialized which caused its APIC ID to be set to 0 (the same APIC ID as BSP).
TEST=boot Debian Linux on PC Engines apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Id06ad4c22a56eb3559e1d584fd0fcac1f95f13e7 --- M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/nb_common.h 2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/39700/1
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8f23e68..8b5a1bf 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> @@ -290,6 +291,7 @@ { u32 nodeid; struct bus *link; + struct resource *res;
nodeid = amdfam16_nodeid(dev); for (link = dev->link_list; link; link = link->next) { @@ -304,6 +306,12 @@ * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + /* NB IOAPIC2 resource */ + res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res->base = IO_APIC2_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) @@ -410,6 +418,7 @@
static void northbridge_init(struct device *dev) { + setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); }
static unsigned long acpi_fill_hest(acpi_hest_t *hest) diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h index 3e78155..46a5c1a 100644 --- a/src/northbridge/amd/pi/nb_common.h +++ b/src/northbridge/amd/pi/nb_common.h @@ -15,5 +15,6 @@ #define __AMD_NB_COMMON_H__
#define DEV_CDB 0x18 +#define IO_APIC2_ADDR 0xfec20000
#endif
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39700 )
Change subject: nb/amd/pi/00730F01: initialize GNB IOAPIC ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39700 )
Change subject: nb/amd/pi/00730F01: initialize GNB IOAPIC ......................................................................
Patch Set 1: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39700 )
Change subject: nb/amd/pi/00730F01: initialize GNB IOAPIC ......................................................................
nb/amd/pi/00730F01: initialize GNB IOAPIC
Northbridge IOAPIC was not being initialized which caused its APIC ID to be set to 0 (the same APIC ID as BSP).
TEST=boot Debian Linux on PC Engines apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Id06ad4c22a56eb3559e1d584fd0fcac1f95f13e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39700 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/nb_common.h 2 files changed, 10 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 05c5142..c87d8ff 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> @@ -290,6 +291,7 @@ { u32 nodeid; struct bus *link; + struct resource *res;
nodeid = amdfam16_nodeid(dev); for (link = dev->link_list; link; link = link->next) { @@ -304,6 +306,12 @@ * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + /* NB IOAPIC2 resource */ + res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res->base = IO_APIC2_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) @@ -410,6 +418,7 @@
static void northbridge_init(struct device *dev) { + setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); }
static unsigned long acpi_fill_hest(acpi_hest_t *hest) diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h index 3e78155..46a5c1a 100644 --- a/src/northbridge/amd/pi/nb_common.h +++ b/src/northbridge/amd/pi/nb_common.h @@ -15,5 +15,6 @@ #define __AMD_NB_COMMON_H__
#define DEV_CDB 0x18 +#define IO_APIC2_ADDR 0xfec20000
#endif
-
Angel Pons (Code Review) -
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)