[S] Change in coreboot[master]: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Kapil Porwal, Ivy Jian, Utkarsh H Patel, Eric Lai, Sukumar Ghorai.

Hello Tarun Tuli, Kapil Porwal, Ivy Jian, Utkarsh H Patel, Eric Lai, Sukumar Ghorai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/70196

to look at the new patch set (#3).

Change subject: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low
......................................................................

mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low

This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based
on the state of the system while `SKL_S0_L` signal is `low` (while
the system is in S0ix). Having `SLP_S0_GATE_R` configured to `high`
makes `SYS_SLP_S0IX_L` remain `high` always and report the wrong
system state to EC.

BUG=b:256807255
TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix.

Signed-off-by: Subrata Banik 
Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce
---
M src/mainboard/google/rex/variants/rex0/gpio.c
1 file changed, 20 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/3