Change in coreboot[master]: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only
Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47760 )
Change subject: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only ......................................................................
src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only
Whole car region is cleared, while only small part needs to be done.
Clear .bss area only
Tested on Facebook FBG1701
Change-Id: I021c2f7d3531c553015fde98d155915f897b434d Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47760/1
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580..e8d5091 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -144,15 +144,16 @@ * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ - - /* coreboot assumes stack/heap region will be zero */ + movl %edx, temp_memory_end + movl %ecx, temp_memory_start + + /* clear .bss section */ cld - movl %ecx, %edi - neg %ecx - /* Clear up to Temp Ram top. */ - add %edx, %ecx + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx shrl $2, %ecx - xorl %eax, %eax rep stosl
/* Need to align stack to 16 bytes at call instruction. Account for
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47760 )
Change subject: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47760/1/src/drivers/intel/fsp1_1/ca... File src/drivers/intel/fsp1_1/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47760/1/src/drivers/intel/fsp1_1/ca... PS1, Line 149: trailing whitespace
Hello build bot (Jenkins), Lee Leahy, Huang Jin, Arthur Heymans, Patrick Rudolph, Wim Vervoorn,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47760
to look at the new patch set (#2).
Change subject: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only ......................................................................
src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only
Whole car region is cleared, while only small part needs to be done.
Clear .bss area only
Tested on Facebook FBG1701
Change-Id: I021c2f7d3531c553015fde98d155915f897b434d Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 5 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47760/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47760 )
Change subject: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47760 )
Change subject: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47760 )
Change subject: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only ......................................................................
src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only
Whole car region is cleared, while only small part needs to be done.
Clear .bss area only
Tested on Facebook FBG1701
Change-Id: I021c2f7d3531c553015fde98d155915f897b434d Signed-off-by: Frans Hendriks fhendriks@eltan.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47760 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 5 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 3be9eb9..b5b47ce 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -145,14 +145,13 @@ * mm1: high 32-bits of TSC value */
- /* coreboot assumes stack/heap region will be zero */ + /* clear .bss section */ cld - movl %ecx, %edi - neg %ecx - /* Clear up to Temp Ram top. */ - add %edx, %ecx + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx shrl $2, %ecx - xorl %eax, %eax rep stosl
/* Need to align stack to 16 bytes at call instruction. Account for
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
build bot (Jenkins) (Code Review)
-
Frans Hendriks (Code Review)
-
Patrick Georgi (Code Review)