Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9738
-gerrit
commit 47515569c041f9f10b0ba64184b6b92b9abe3dfd Author: Vadim Bendebury vbendeb@chromium.org Date: Fri Jan 9 16:54:19 2015 -0800
uart: pass register width in the coreboot table
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width.
Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART.
BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board
Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury vbendeb@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/cpu/allwinner/a10/uart_console.c | 1 + src/cpu/ti/am335x/uart.c | 1 + src/drivers/uart/oxpcie_early.c | 1 + src/drivers/uart/pl011.c | 1 + src/drivers/uart/uart8250io.c | 1 + src/include/boot/coreboot_tables.h | 1 + src/lib/coreboot_table.c | 1 + src/mainboard/emulation/qemu-riscv/uart.c | 1 + src/soc/imgtec/pistachio/uart.c | 1 + src/soc/nvidia/tegra124/uart.c | 1 + src/soc/nvidia/tegra132/uart.c | 1 + src/soc/rockchip/rk3288/uart.c | 1 + src/soc/samsung/exynos5250/uart.c | 1 + src/soc/samsung/exynos5420/uart.c | 1 + 14 files changed, 14 insertions(+)
diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index ff86348..35bff79 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -34,6 +34,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 5756834..a886e50 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -195,6 +195,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 2; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index 343056c..9daafc5 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -99,6 +99,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index e2db877..aa55c68 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -47,6 +47,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 60a8d86..2cb586e 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -142,6 +142,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_IO_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 74851b2..7b5da64 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -159,6 +159,7 @@ struct lb_serial { uint32_t type; uint32_t baseaddr; uint32_t baud; + uint32_t regwidth; };
#define LB_TAG_CONSOLE 0x0010 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6450b59..b62f452 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -115,6 +115,7 @@ void lb_add_serial(struct lb_serial *new_serial, void *data) serial->type = new_serial->type; serial->baseaddr = new_serial->baseaddr; serial->baud = new_serial->baud; + serial->regwidth = new_serial->regwidth; }
void lb_add_console(uint16_t consoletype, void *data) diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 6647cde..207f441 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -53,6 +53,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = 0x3f8; serial.baud = 115200; + serial.regwidth = 1; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index b589289..ff91459 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -179,6 +179,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 4af00e9..a25540b 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -141,6 +141,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c index 17e1a53..3a9ac22 100644 --- a/src/soc/nvidia/tegra132/uart.c +++ b/src/soc/nvidia/tegra132/uart.c @@ -154,6 +154,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c index 01759fe..7685ff9 100644 --- a/src/soc/rockchip/rk3288/uart.c +++ b/src/soc/rockchip/rk3288/uart.c @@ -160,6 +160,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 997aa0d..c23cfed 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -195,6 +195,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index e2be882..74e5067 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -186,6 +186,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
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Patrick Georgi