Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock - coreboot-gerrit

27 Jun 2019


      Steve Mooney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 )
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Patch Set 14:
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Patch Set 14: Code-Review+1
My mistake on the previous comment.  Looks good.
Curious if you meant keep SPI in the function name?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 14
Gerrit-Owner: Julien Viard de Galbert coreboot-review-ju@vdg.name
Gerrit-Reviewer: David Guckian david.guckian@intel.com
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