Change in coreboot[master]: amdfam10: Drop spurious #ifdef __PRE_RAM__

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34930 )

Change subject: amdfam10: Drop spurious #ifdef __PRE_RAM__
......................................................................

amdfam10: Drop spurious #ifdef __PRE_RAM__

Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki 
---
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdfam10/amdfam10_util.c
M src/northbridge/amd/amdfam10/util.c
M src/southbridge/amd/cimx/sb800/fan.h
M src/southbridge/amd/cimx/sb900/cfg.c
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/smbus.h
M src/southbridge/nvidia/mcp55/mcp55.h
9 files changed, 10 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34930/1

diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 321e87d..96938b2 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -922,13 +922,11 @@

#include "nums.h"

-#ifdef __PRE_RAM__
 #if NODE_NUMS == 64
     #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 #else
     #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
 #endif
-#endif

/* Include wrapper for MCT (works for DDR2 or DDR3) */
 #include <northbridge/amd/amdmct/wrappers/mcti.h>
@@ -989,11 +987,8 @@
    struct DCTStatStruc DCTstatA[NODE_NUMS];
 } __packed;

-#ifndef __PRE_RAM__
 struct device *get_node_pci(u32 nodeid, u32 fn);
-#endif

-#ifdef __PRE_RAM__
 void showallroutes(int level, pci_devfn_t dev);

void setup_resource_map_offset(const u32 *register_values, u32 max, u32
@@ -1017,8 +1012,6 @@
 u8 get_sbbusn(u8 sblk);
 void set_bios_reset(void);

-#endif
-
 #include "northbridge/amd/amdht/porting.h"
 BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);

diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
index 292049e..3e8c2fb 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -14,15 +14,14 @@
  * GNU General Public License for more details.
  */

-#include <console/console.h>
-
 #include <arch/cpu.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
 #include "raminit.h"
 #include <northbridge/amd/amdmct/amddefs.h>

-#ifndef __PRE_RAM__
-#include <include/device/pci_ops.h>
-#include <include/device/pci_def.h>
+#ifndef __SIMPLE_DEVICE__
 u32 Get_NB32(u32 dev, u32 reg)
 {
    return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg);
diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c
index 39c2bfb..ed5556f 100644
--- a/src/northbridge/amd/amdfam10/util.c
+++ b/src/northbridge/amd/amdfam10/util.c
@@ -21,11 +21,10 @@
  * It can be called after RAM is set up by including amdfam10.h and enabling the
  * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc.
  */
-#ifndef __PRE_RAM__
 #include <console/console.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
-#endif
+
 #include "amdfam10.h"

/* Function 1 */
diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h
index f31e486..3734da1 100644
--- a/src/southbridge/amd/cimx/sb800/fan.h
+++ b/src/southbridge/amd/cimx/sb800/fan.h
@@ -16,10 +16,10 @@
 #ifndef _SB800_FAN_H_
 #define _SB800_FAN_H_

-#ifndef __PRE_RAM__
+#include <device/device.h>
+
 void init_sb800_IMC_fans(struct device *dev);
 void init_sb800_MANUAL_fans(struct device *dev);
-#endif

/* Fan Register Definitions */
 #define FAN_0_OFFSET				0x00
diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c
index 353d577..2e4173f 100644
--- a/src/southbridge/amd/cimx/sb900/cfg.c
+++ b/src/southbridge/amd/cimx/sb900/cfg.c
@@ -243,15 +243,13 @@
    sb_config->PciClks								= SB_PCI_CLOCK_RESERVED;
    sb_config->hwm.hwmEnable						= 0x0;

-#ifndef __PRE_RAM__
    /* ramstage cimx config here */
-	if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
+	if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) {
    	sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
    }

//sb_config->
-#endif //!__PRE_RAM__
-    printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
+	printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
 }

void SbPowerOnInit_Config(AMDSBCFG *sb_config)
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h
index 4517dda..e1c6f66 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.h
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.h
@@ -20,11 +20,8 @@
 #include <device/device.h>
 #include "chip.h"

-#ifndef __PRE_RAM__
 void bcm5785_enable(struct device *dev);
-#else
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif

void bcm5785_set_subsystem(struct device *dev, unsigned int vendor,
    		       unsigned int device);
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index 5505691..6812b5b 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -26,8 +26,6 @@
 #define CK804B_BUSN 0x80
 #define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)

-#ifdef __PRE_RAM__
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif

#endif
diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h
index cec62b3..618e177 100644
--- a/src/southbridge/nvidia/ck804/smbus.h
+++ b/src/southbridge/nvidia/ck804/smbus.h
@@ -49,7 +49,6 @@
    return -3;
 }

-#ifndef __PRE_RAM__
 static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 {
    unsigned char global_status_register, byte;
@@ -114,7 +113,6 @@

return 0;
 }
-#endif

static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
    		      unsigned address)
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 8d595c9..944d35a 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -24,11 +24,10 @@
 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif

-#ifndef __PRE_RAM__
 #include "chip.h"
 void mcp55_enable(struct device *dev);
 extern struct pci_operations mcp55_pci_ops;
-#else
+
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
 void enable_smbus(void);
 int smbus_recv_byte(unsigned device);
@@ -40,6 +39,5 @@
 int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);
 int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,
    	unsigned char val);
-#endif

#endif

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34930 )

Change subject: amdfam10: Drop spurious #ifdef __PRE_RAM__
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/34930/1/src/southbridge/amd/cimx/sb... 
File src/southbridge/amd/cimx/sb900/cfg.c:

https://review.coreboot.org/c/coreboot/+/34930/1/src/southbridge/amd/cimx/sb... 
PS1, Line 247: 	if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/34930/1/src/southbridge/amd/cimx/sb... 
PS1, Line 252: 	printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
Prefer using '"%s...", __func__' to using 'sb900_cimx_config', this function's name, in a string

[Kyösti Mälkki (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34930

to look at the new patch set (#2).

Change subject: amdfam10: Drop spurious #ifdef __PRE_RAM__
......................................................................

amdfam10: Drop spurious #ifdef __PRE_RAM__

Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki 
---
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdfam10/amdfam10_util.c
M src/northbridge/amd/amdfam10/util.c
M src/southbridge/amd/cimx/sb800/fan.h
M src/southbridge/amd/cimx/sb900/cfg.c
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/smbus.h
M src/southbridge/nvidia/mcp55/chip.h
M src/southbridge/nvidia/mcp55/mcp55.h
10 files changed, 17 insertions(+), 33 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34930/2

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34930 )

Change subject: amdfam10: Drop spurious #ifdef __PRE_RAM__
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/34930/2/src/southbridge/amd/cimx/sb... 
File src/southbridge/amd/cimx/sb900/cfg.c:

https://review.coreboot.org/c/coreboot/+/34930/2/src/southbridge/amd/cimx/sb... 
PS2, Line 247: 	if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/34930/2/src/southbridge/amd/cimx/sb... 
PS2, Line 252: 	printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
Prefer using '"%s...", __func__' to using 'sb900_cimx_config', this function's name, in a string

[Kyösti Mälkki (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34930

to look at the new patch set (#3).

Change subject: amdfam10: Drop spurious #ifdef __PRE_RAM__
......................................................................

amdfam10: Drop spurious #ifdef __PRE_RAM__

Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki 
---
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdfam10/amdfam10_util.c
M src/northbridge/amd/amdfam10/util.c
M src/southbridge/amd/cimx/sb800/fan.h
M src/southbridge/amd/cimx/sb900/cfg.c
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/smbus.h
M src/southbridge/nvidia/mcp55/chip.h
M src/southbridge/nvidia/mcp55/ide.c
M src/southbridge/nvidia/mcp55/mcp55.h
M src/southbridge/nvidia/mcp55/nic.c
M src/southbridge/nvidia/mcp55/sata.c
13 files changed, 26 insertions(+), 33 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34930/3

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34930 )

Change subject: amdfam10: Drop spurious #ifdef __PRE_RAM__
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/34930/3/src/southbridge/amd/cimx/sb... 
File src/southbridge/amd/cimx/sb900/cfg.c:

https://review.coreboot.org/c/coreboot/+/34930/3/src/southbridge/amd/cimx/sb... 
PS3, Line 247: 	if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/34930/3/src/southbridge/amd/cimx/sb... 
PS3, Line 252: 	printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
Prefer using '"%s...", __func__' to using 'sb900_cimx_config', this function's name, in a string

Change in coreboot[master]: amdfam10: Remove use of __PRE_RAM__

[Kyösti Mälkki (Code Review)]

Hello Arthur Heymans, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34930

to look at the new patch set (#6).

Change subject: amdfam10: Remove use of __PRE_RAM__
......................................................................

amdfam10: Remove use of __PRE_RAM__

Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/quadcore/quadcore_id.c
M src/include/cpu/amd/multicore.h
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdfam10/amdfam10_util.c
M src/northbridge/amd/amdfam10/util.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/southbridge/amd/amd8111/amd8111.h
M src/southbridge/amd/sb700/sb700.h
M src/southbridge/amd/sb800/sb800.h
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/smbus.h
M src/southbridge/nvidia/mcp55/chip.h
M src/southbridge/nvidia/mcp55/ide.c
M src/southbridge/nvidia/mcp55/mcp55.h
M src/southbridge/nvidia/mcp55/nic.c
M src/southbridge/nvidia/mcp55/sata.c
18 files changed, 46 insertions(+), 70 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34930/6

Change in coreboot[master]: amdfam10: Remove use of __PRE_RAM__

[Kyösti Mälkki (Code Review)]

Hello Arthur Heymans, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34930

to look at the new patch set (#7).

Change subject: amdfam10: Remove use of __PRE_RAM__
......................................................................

amdfam10: Remove use of __PRE_RAM__

Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/quadcore/quadcore_id.c
M src/include/cpu/amd/multicore.h
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdfam10/amdfam10_util.c
M src/northbridge/amd/amdfam10/util.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/southbridge/amd/amd8111/amd8111.h
M src/southbridge/amd/amd8111/ide.c
M src/southbridge/amd/amd8111/nic.c
M src/southbridge/amd/sb700/ide.c
M src/southbridge/amd/sb700/sb700.c
M src/southbridge/amd/sb700/sb700.h
M src/southbridge/amd/sb800/ide.c
M src/southbridge/amd/sb800/sata.c
M src/southbridge/amd/sb800/sb800.c
M src/southbridge/amd/sb800/sb800.h
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/smbus.h
M src/southbridge/nvidia/mcp55/chip.h
M src/southbridge/nvidia/mcp55/ide.c
M src/southbridge/nvidia/mcp55/mcp55.h
M src/southbridge/nvidia/mcp55/nic.c
M src/southbridge/nvidia/mcp55/sata.c
25 files changed, 61 insertions(+), 88 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34930/7

Change in coreboot[master]: amdfam10: Remove use of __PRE_RAM__

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34930 )

Change subject: amdfam10: Remove use of __PRE_RAM__
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34930/7/src/northbridge/amd/amdmct/... 
File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:

https://review.coreboot.org/c/coreboot/+/34930/7/src/northbridge/amd/amdmct/... 
PS7, Line 277: static void wrmsr_uint64_t(unsigned long index, uint64_t value) {
open brace '{' following function definitions go on the next line

Change in coreboot[master]: amdfam10: Remove use of __PRE_RAM__

[Kyösti Mälkki (Code Review)]

Hello Arthur Heymans, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34930

to look at the new patch set (#8).

Change subject: amdfam10: Remove use of __PRE_RAM__
......................................................................

amdfam10: Remove use of __PRE_RAM__

Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/quadcore/quadcore_id.c
M src/include/cpu/amd/multicore.h
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdfam10/amdfam10_util.c
M src/northbridge/amd/amdfam10/util.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/southbridge/amd/amd8111/amd8111.h
M src/southbridge/amd/amd8111/ide.c
M src/southbridge/amd/amd8111/nic.c
M src/southbridge/amd/sb700/ide.c
M src/southbridge/amd/sb700/sb700.c
M src/southbridge/amd/sb700/sb700.h
M src/southbridge/amd/sb800/ide.c
M src/southbridge/amd/sb800/sata.c
M src/southbridge/amd/sb800/sb800.c
M src/southbridge/amd/sb800/sb800.h
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/smbus.h
M src/southbridge/nvidia/mcp55/chip.h
M src/southbridge/nvidia/mcp55/ide.c
M src/southbridge/nvidia/mcp55/mcp55.h
M src/southbridge/nvidia/mcp55/nic.c
M src/southbridge/nvidia/mcp55/sata.c
25 files changed, 62 insertions(+), 88 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34930/8

Change in coreboot[master]: amdfam10: Remove use of __PRE_RAM__

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34930 )

Change subject: amdfam10: Remove use of __PRE_RAM__
......................................................................

Patch Set 8: Code-Review+2

LGTM

Change in coreboot[master]: amdfam10: Remove use of __PRE_RAM__

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34930 )

Change subject: amdfam10: Remove use of __PRE_RAM__
......................................................................

amdfam10: Remove use of __PRE_RAM__

Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34930
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/quadcore/quadcore_id.c
M src/include/cpu/amd/multicore.h
M src/northbridge/amd/amdfam10/amdfam10.h
M src/northbridge/amd/amdfam10/amdfam10_util.c
M src/northbridge/amd/amdfam10/util.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/southbridge/amd/amd8111/amd8111.h
M src/southbridge/amd/amd8111/ide.c
M src/southbridge/amd/amd8111/nic.c
M src/southbridge/amd/sb700/ide.c
M src/southbridge/amd/sb700/sb700.c
M src/southbridge/amd/sb700/sb700.h
M src/southbridge/amd/sb800/ide.c
M src/southbridge/amd/sb800/sata.c
M src/southbridge/amd/sb800/sb800.c
M src/southbridge/amd/sb800/sb800.h
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/smbus.h
M src/southbridge/nvidia/mcp55/chip.h
M src/southbridge/nvidia/mcp55/ide.c
M src/southbridge/nvidia/mcp55/mcp55.h
M src/southbridge/nvidia/mcp55/nic.c
M src/southbridge/nvidia/mcp55/sata.c
25 files changed, 62 insertions(+), 88 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
index 1433e07..582fba9 100644
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
@@ -68,7 +68,7 @@
    if (is_fam15h()) {
    	enable_cc6 = 0;

-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
    	if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
    		enable_cc6 = 1;
 #else
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index 5afb051..f3e9f4b 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -17,11 +17,9 @@

#include <arch/cpu.h>
+#include <cpu/amd/msr.h>
 #include <cpu/amd/multicore.h>
 #include <device/pci_ops.h>
-#ifdef __PRE_RAM__
-#include <cpu/amd/msr.h>
-#endif

//called by bus_cpu_scan too
 u32 read_nb_cfg_54(void)
@@ -48,7 +46,7 @@
    uint32_t family;
    uint32_t model;

-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
    f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
 #else
    f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
@@ -115,7 +113,7 @@
    	uint32_t f5x84;
    	uint8_t core_count;

-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
    	f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84);
 #else
    	f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84);
diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h
index b868093..79bea66 100644
--- a/src/include/cpu/amd/multicore.h
+++ b/src/include/cpu/amd/multicore.h
@@ -17,6 +17,7 @@
 #define CPU_AMD_QUADCORE_H

#include <stdint.h>
+#include <device/device.h>

u32 read_nb_cfg_54(void);

@@ -29,17 +30,14 @@
 struct node_core_id get_node_core_id(u32 nb_cfg_54);
 struct node_core_id get_node_core_id_x(void);

-#if !defined(__PRE_RAM__)
-struct device;
 u32 get_apicid_base(u32 ioapic_num);
 void amd_sibling_init(struct device *cpu);
-#else
+
 void wait_all_core0_started(void);
 void wait_all_other_cores_started(u32 bsp_apicid);
 void wait_all_aps_started(u32 bsp_apicid);
 void wait_all_other_cores_stopped(uint32_t bsp_apicid);
 void allow_all_aps_stop(u32 bsp_apicid);
-#endif
 u32 get_initial_apicid(void);

#endif /* CPU_AMD_QUADCORE_H */
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 321e87d..96938b2 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -922,13 +922,11 @@

#include "nums.h"

-#ifdef __PRE_RAM__
 #if NODE_NUMS == 64
     #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 #else
     #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
 #endif
-#endif

/* Include wrapper for MCT (works for DDR2 or DDR3) */
 #include <northbridge/amd/amdmct/wrappers/mcti.h>
@@ -989,11 +987,8 @@
    struct DCTStatStruc DCTstatA[NODE_NUMS];
 } __packed;

-#ifndef __PRE_RAM__
 struct device *get_node_pci(u32 nodeid, u32 fn);
-#endif

-#ifdef __PRE_RAM__
 void showallroutes(int level, pci_devfn_t dev);

void setup_resource_map_offset(const u32 *register_values, u32 max, u32
@@ -1017,8 +1012,6 @@
 u8 get_sbbusn(u8 sblk);
 void set_bios_reset(void);

-#endif
-
 #include "northbridge/amd/amdht/porting.h"
 BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);

diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
index 292049e..3e8c2fb 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -14,15 +14,14 @@
  * GNU General Public License for more details.
  */

-#include <console/console.h>
-
 #include <arch/cpu.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
 #include "raminit.h"
 #include <northbridge/amd/amdmct/amddefs.h>

-#ifndef __PRE_RAM__
-#include <include/device/pci_ops.h>
-#include <include/device/pci_def.h>
+#ifndef __SIMPLE_DEVICE__
 u32 Get_NB32(u32 dev, u32 reg)
 {
    return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg);
diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c
index 39c2bfb..ed5556f 100644
--- a/src/northbridge/amd/amdfam10/util.c
+++ b/src/northbridge/amd/amdfam10/util.c
@@ -21,11 +21,10 @@
  * It can be called after RAM is set up by including amdfam10.h and enabling the
  * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc.
  */
-#ifndef __PRE_RAM__
 #include <console/console.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
-#endif
+
 #include "amdfam10.h"

/* Function 1 */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 1517398..1fdbc16 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -79,7 +79,7 @@
 {
    if (is_fam15h()) {
    	uint32_t dword;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
    	pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
    	struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
@@ -108,7 +108,7 @@
 {
    if (is_fam15h()) {
    	uint32_t dword;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
    	pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
    	struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
@@ -158,7 +158,7 @@
 {
    if (is_fam15h()) {
    	uint32_t dword;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
    	pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
    	struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
@@ -253,7 +253,6 @@
    return persistent_data;
 }

-#ifdef __PRE_RAM__
 int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
 {
    struct amd_s3_persistent_data *persistent_data;
@@ -269,14 +268,20 @@

return 0;
 }
-#endif

-#ifdef __RAMSTAGE__
 static uint64_t rdmsr_uint64_t(unsigned long index) {
    msr_t msr = rdmsr(index);
    return (((uint64_t)msr.hi) << 32) | ((uint64_t)msr.lo);
 }

+static void wrmsr_uint64_t(unsigned long index, uint64_t value)
+{
+	msr_t msr;
+	msr.hi = (value & 0xffffffff00000000ULL) >> 32;
+	msr.lo = (value & 0xffffffff);
+	wrmsr(index, msr);
+}
+
 static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node,
    				   uint8_t dct, uint8_t nb_pstate,
    				   uint32_t reg)
@@ -557,7 +562,7 @@
    	}
    }
 }
-#else
+
 static void write_config32_dct_nbpstate(pci_devfn_t dev, uint8_t node,
    				uint8_t dct, uint8_t nb_pstate,
    				uint32_t reg, uint32_t value)
@@ -615,15 +620,6 @@

return write_amd_dct_index_register(dev, index_ctl_reg, index, value);
 }
-#endif
-
-#ifdef __PRE_RAM__
-static void wrmsr_uint64_t(unsigned long index, uint64_t value) {
-	msr_t msr;
-	msr.hi = (value & 0xffffffff00000000ULL) >> 32;
-	msr.lo = (value & 0xffffffff);
-	wrmsr(index, msr);
-}

void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only)
 {
@@ -1130,9 +1126,7 @@
    	}
    }
 }
-#endif

-#ifdef __RAMSTAGE__
 int8_t save_mct_information_to_nvram(void)
 {
    uint8_t nvram;
@@ -1206,7 +1200,6 @@

return 0;
 }
-#endif

int8_t restore_mct_information_from_nvram(uint8_t training_only)
 {
diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h
index a984143..447edf9 100644
--- a/src/southbridge/amd/amd8111/amd8111.h
+++ b/src/southbridge/amd/amd8111/amd8111.h
@@ -14,14 +14,9 @@
 #ifndef AMD8111_H
 #define AMD8111_H

-#include "chip.h"
+#include <device/device.h>

-#ifndef __SIMPLE_DEVICE__
 void amd8111_enable(struct device *dev);
-#endif
-
-#ifdef __PRE_RAM__
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif

#endif /* AMD8111_H */
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c
index 420e28e..49f9d15 100644
--- a/src/southbridge/amd/amd8111/ide.c
+++ b/src/southbridge/amd/amd8111/ide.c
@@ -17,6 +17,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "amd8111.h"
+#include "chip.h"

static void ide_init(struct device *dev)
 {
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
index adf8af0..a4abd03 100644
--- a/src/southbridge/amd/amd8111/nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
@@ -21,7 +21,7 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include "amd8111.h"
-
+#include "chip.h"

#define CMD3		0x54

diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c
index 0b11db3..070ee67 100644
--- a/src/southbridge/amd/sb700/ide.c
+++ b/src/southbridge/amd/sb700/ide.c
@@ -22,6 +22,7 @@
 #include <types.h>

#include "sb700.h"
+#include "chip.h"

static void ide_init(struct device *dev)
 {
diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c
index 1836f34..1eaf347 100644
--- a/src/southbridge/amd/sb700/sb700.c
+++ b/src/southbridge/amd/sb700/sb700.c
@@ -22,6 +22,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "sb700.h"
+#include "chip.h"

static struct device *find_sm_dev(struct device *dev, u32 devfn)
 {
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 156522e..4b863a0 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -17,7 +17,8 @@
 #ifndef SB700_H
 #define SB700_H

-#include "chip.h"
+#include <types.h>
+#include <device/device.h>

/* Power management index/data registers */
 #define BIOSRAM_INDEX	0xcd4
@@ -37,14 +38,12 @@
 #define ACPI_CPU_CONTROL	(SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */
 #define ACPI_CPU_P_LVL2		(ACPI_CPU_CONTROL + 0x4)    /* 1 byte */

-extern void pm_iowrite(u8 reg, u8 value);
-extern u8 pm_ioread(u8 reg);
-extern void pm2_iowrite(u8 reg, u8 value);
-extern u8 pm2_ioread(u8 reg);
-#ifndef __SIMPLE_DEVICE__
-extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask,
-			       u32 val);
-#endif
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);

#define REV_SB700_A11	0x11
 #define REV_SB700_A12	0x12
@@ -58,11 +57,7 @@
  * The differentiate is 0x28, isn't it? */
 #define get_sb700_revision(sm_dev)	(pci_read_config8((sm_dev), 0x08) - 0x28)

-#ifndef __SIMPLE_DEVICE__
-void sb7xx_51xx_enable(struct device *dev);
-#endif

-#ifdef __PRE_RAM__
 void sb7xx_51xx_lpc_port80(void);
 void sb7xx_51xx_pci_port80(void);
 void sb7xx_51xx_lpc_init(void);
@@ -71,14 +66,12 @@
 void sb7xx_51xx_early_setup(void);
 void sb7xx_51xx_before_pci_init(void);
 uint16_t sb7xx_51xx_decode_last_reset(void);
-#else
-#include <device/pci.h>
-#include <device/pci_ops.h>
+
+
 /* allow override in mainboard.c */
 void sb7xx_51xx_setup_sata_phys(struct device *dev);
 void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5);
-
-#endif
+void sb7xx_51xx_enable(struct device *dev);

void set_lpc_sticky_ctl(bool enable);

@@ -86,4 +79,5 @@
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);

void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn);
+
 #endif /* SB700_H */
diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c
index fddb48c..77e2f5e 100644
--- a/src/southbridge/amd/sb800/ide.c
+++ b/src/southbridge/amd/sb800/ide.c
@@ -18,6 +18,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "sb800.h"
+#include "chip.h"

static void ide_init(struct device *dev)
 {
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index 48a8740..8611272 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -22,6 +22,7 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include "sb800.h"
+#include "chip.h"

static int sata_drive_detect(int portnum, u16 iobar)
 {
diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c
index 801cc65..c7efaec 100644
--- a/src/southbridge/amd/sb800/sb800.c
+++ b/src/southbridge/amd/sb800/sb800.c
@@ -23,6 +23,7 @@
 #include <device/pci_ops.h>
 #include "sb800.h"
 #include "smbus.h"
+#include "chip.h"

static struct device *find_sm_dev(struct device *dev, u32 devfn)
 {
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index 3715a3a..07c78ec 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -17,7 +17,8 @@
 #ifndef SB800_H
 #define SB800_H

-#include "chip.h"
+#include <types.h>
+#include <device/device.h>

/* Power management index/data registers */
 #define BIOSRAM_INDEX	0xcd4
@@ -42,15 +43,11 @@
 void pm2_iowrite(u8 reg, u8 value);
 u8 pm2_ioread(u8 reg);

-#ifndef __SIMPLE_DEVICE__
 void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
-#endif

#define REV_SB800_A11	0x11
 #define REV_SB800_A12	0x12

-
-#ifdef __PRE_RAM__
 void sb800_lpc_port80(void);
 void sb800_pci_port80(void);
 void sb800_clk_output_48Mhz(void);
@@ -58,8 +55,6 @@
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);

-#else
 void sb800_enable(struct device *dev);
-#endif

#endif /* SB800_H */
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h
index 4517dda..e1c6f66 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.h
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.h
@@ -20,11 +20,8 @@
 #include <device/device.h>
 #include "chip.h"

-#ifndef __PRE_RAM__
 void bcm5785_enable(struct device *dev);
-#else
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif

void bcm5785_set_subsystem(struct device *dev, unsigned int vendor,
    		       unsigned int device);
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index 5505691..6812b5b 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -26,8 +26,6 @@
 #define CK804B_BUSN 0x80
 #define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)

-#ifdef __PRE_RAM__
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif

#endif
diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h
index cec62b3..bf0ff3c 100644
--- a/src/southbridge/nvidia/ck804/smbus.h
+++ b/src/southbridge/nvidia/ck804/smbus.h
@@ -49,7 +49,9 @@
    return -3;
 }

-#ifndef __PRE_RAM__
+
+/* Platform has severe issues placing non-inlined functions in headers. */
+#if ENV_RAMSTAGE
 static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 {
    unsigned char global_status_register, byte;
@@ -114,7 +116,7 @@

return 0;
 }
-#endif
+#endif /* ENV_RAMSTAGE */

static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
    		      unsigned address)
diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h
index adf4725..4bc8428 100644
--- a/src/southbridge/nvidia/mcp55/chip.h
+++ b/src/southbridge/nvidia/mcp55/chip.h
@@ -18,8 +18,6 @@
 #ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
 #define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H

-#include <device/device.h>
-
 struct southbridge_nvidia_mcp55_config
 {
    unsigned int ide0_enable : 1;
diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c
index 797b9d8..36e20b4 100644
--- a/src/southbridge/nvidia/mcp55/ide.c
+++ b/src/southbridge/nvidia/mcp55/ide.c
@@ -22,6 +22,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+
+#include "chip.h"
 #include "mcp55.h"

static void ide_init(struct device *dev)
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 8d595c9..ac68909 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -24,13 +24,17 @@
 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif

-#ifndef __PRE_RAM__
-#include "chip.h"
+#ifndef __ROMCC__
+#include <device/device.h>
 void mcp55_enable(struct device *dev);
 extern struct pci_operations mcp55_pci_ops;
-#else
+#endif
+
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
 void enable_smbus(void);
+
+/* Concflict declarations with <device/smbus.h>. */
+#if !ENV_RAMSTAGE
 int smbus_recv_byte(unsigned device);
 int smbus_send_byte(unsigned device, unsigned char val);
 int smbus_read_byte(unsigned device, unsigned address);
@@ -40,6 +44,6 @@
 int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);
 int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,
    	unsigned char val);
-#endif
+#endif /* !ENV_RAMSTAGE */

#endif
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index 4ee3a3b..af4df44 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -25,6 +25,8 @@
 #include <device/pci_ops.h>
 #include <device/mmio.h>
 #include <delay.h>
+
+#include "chip.h"
 #include "mcp55.h"

static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c
index 27f6073..9f70890 100644
--- a/src/southbridge/nvidia/mcp55/sata.c
+++ b/src/southbridge/nvidia/mcp55/sata.c
@@ -23,6 +23,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>

+#include "chip.h"
 #include "mcp55.h"

static void sata_init(struct device *dev)