Change in coreboot[master]: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35994 )

Change subject: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
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Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35994/9/src/cpu/x86/mtrr/xip_cache.... 
File src/cpu/x86/mtrr/xip_cache.c:

https://review.coreboot.org/c/coreboot/+/35994/9/src/cpu/x86/mtrr/xip_cache.... 
PS9, Line 58: 	if (end < ALIGN_UP(base, mtrr_mask_size) &&
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