Change in coreboot[master]: soc/intel: Use CONFIG_HPET_ADDRESS value

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36468 )

Change subject: soc/intel: Use CONFIG_HPET_ADDRESS value
......................................................................

soc/intel: Use CONFIG_HPET_ADDRESS value

Change-Id: I50dacf7fe395788b3db719740888bf14da74d8f8
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/baytrail/acpi/lpc.asl
M src/soc/intel/braswell/acpi/lpc.asl
M src/soc/intel/broadwell/acpi/lpc.asl
M src/soc/intel/fsp_baytrail/acpi/lpc.asl
M src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
5 files changed, 8 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/36468/1

diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index 00aac51..7cdf1aa 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -59,7 +59,7 @@

Name(_CRS, ResourceTemplate()
    	{
-			Memory32Fixed(ReadOnly, 0xfed00000, 0x400)
+			Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
    	})
    }

diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index 9caa8f1..a8604d6 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -71,7 +71,7 @@

Name(_CRS, ResourceTemplate()
    	{
-			Memory32Fixed(ReadOnly, 0xfed00000, 0x400)
+			Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
    	})
    }
 #endif
diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl
index 70dd6e5..ca44c5c 100644
--- a/src/soc/intel/broadwell/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/acpi/lpc.asl
@@ -74,7 +74,7 @@

Name (BUF0, ResourceTemplate()
    	{
-			Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)
+			Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
    	})

Method (_STA, 0)	// Device Status
@@ -99,15 +99,15 @@
    				_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)

If (Lequal(HPAS, 1)) {
-					Store(0xfed01000, HPT0)
+					Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0)
    			}

If (Lequal(HPAS, 2)) {
-					Store(0xfed02000, HPT0)
+					Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0)
    			}

If (Lequal(HPAS, 3)) {
-					Store(0xfed03000, HPT0)
+					Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0)
    			}
    		}

diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
index 00aac51..7cdf1aa 100644
--- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
@@ -59,7 +59,7 @@

Name(_CRS, ResourceTemplate()
    	{
-			Memory32Fixed(ReadOnly, 0xfed00000, 0x400)
+			Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
    	})
    }

diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
index 6a7a2f1..ef1e655 100644
--- a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
+++ b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
@@ -44,7 +44,7 @@

Name(_CRS, ResourceTemplate()
    	{
-			Memory32Fixed(ReadOnly, 0xfed00000, 0x400)
+			Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
    	})
    }

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36468 )

Change subject: soc/intel: Use CONFIG_HPET_ADDRESS value
......................................................................

Abandoned

see https://review.coreboot.org/c/coreboot/+/36458/4