Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: [WIP] lib/stage_cache: Rename Kconfig options ......................................................................
[WIP] lib/stage_cache: Rename Kconfig options
Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/Kconfig M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/smmrelocate.c D src/cpu/intel/haswell/stage_cache.c M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_2065x/model_2065x.h D src/cpu/intel/model_2065x/stage_cache.c M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/model_206ax.h D src/cpu/intel/model_206ax/stage_cache.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/stage_cache.h M src/lib/Makefile.inc M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/Makefile.inc M src/northbridge/intel/gm45/ram_calc.c D src/northbridge/intel/gm45/stage_cache.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/Makefile.inc M src/northbridge/intel/i945/ram_calc.c D src/northbridge/intel/i945/stage_cache.c M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/ram_calc.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/ram_calc.c D src/northbridge/intel/pineview/stage_cache.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/ram_calc.c M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/ram_calc.c D src/northbridge/intel/x4x/stage_cache.c M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/memmap.c D src/soc/intel/baytrail/stage_cache.c M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/memmap.c D src/soc/intel/broadwell/stage_cache.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 54 files changed, 157 insertions(+), 394 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/34664/1
diff --git a/src/Kconfig b/src/Kconfig index 2bb5bfe..b64af11 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -250,12 +250,24 @@ wake. When selecting this option the romstage is responsible for determing a stack location to use for loading the ramstage.
-config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - depends on RELOCATABLE_RAMSTAGE +config TSEG_STAGE_CACHE bool + default y + depends on RELOCATABLE_RAMSTAGE + depends on !NO_STAGE_CACHE && SMM_TSEG help - The relocated ramstage is saved in an area specified by the - by the board and/or chipset. + The option enables external stage cache support for platform. Platform + can relocate postcar(if enable), ramstage in an area specified by the + board and/or chipset. + +config CBMEM_STAGE_CACHE + bool "Cache stages in CBMEM" + depends on RELOCATABLE_RAMSTAGE + depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE + help + The option enables internal (inside cbmem) stage cache support for + platform. Platform can relocate romstage, postcar, ramstage in an + area inside cbmem.
config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index f960648..d46a422 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -7,12 +7,8 @@ postcar-y += tsc_freq.c
ramstage-y += acpi.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - smm-y += finalize.c smm-y += tsc_freq.c
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cd8d5cb..cfd9d45 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -118,15 +118,9 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0
-/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3948cfe..3a4a0a7 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -250,7 +250,7 @@ params->ied_size = tseg_size - params->smram_size;
/* Adjust available SMM handler memory size. */ - params->smram_size -= RESERVED_SMM_SIZE; + params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
/* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c deleted file mode 100644 index 009cc09..0000000 --- a/src/cpu/intel/haswell/stage_cache.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include "haswell.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); -} diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 089b3fe..a3a58b6 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -21,7 +21,6 @@ select CPU_INTEL_COMMON select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 9a11b06..1f6d1a2 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -19,10 +19,6 @@
smm-y += finalize.c
-romstage-y += stage_cache.c -ramstage-y += stage_cache.c -postcar-y += stage_cache.c - cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index eab2dd5..2f3584a 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -80,16 +80,9 @@ int cpu_config_tdp_levels(void); #endif
-/* - * Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. - */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE) -# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE" +#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) +# error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c deleted file mode 100644 index ab8ac97..0000000 --- a/src/cpu/intel/model_2065x/stage_cache.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> -#include "model_2065x.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + RESERVED_SMM_OFFSET); -} diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 2af63d6..ced3340 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,7 +19,6 @@ #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index f5de8c3..e723d74 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -24,10 +24,6 @@
smm-y += finalize.c
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index c0d2434..2dc9293 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -81,17 +81,9 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10
-/* - * Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. - */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c deleted file mode 100644 index 26dc5e0..0000000 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include "model_206ax.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); -} diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 986929c..d8021e6 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -121,7 +121,7 @@ }
/* Adjust available SMM handler memory size. */ - if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) { + if (CONFIG(TSEG_STAGE_CACHE)) { ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE); params->smram_size -= CONFIG_SMM_RESERVED_SIZE; } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 3483c0c..f83c924 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -32,8 +32,7 @@ STAGE_S3_DATA, };
-#if CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) \ - || CONFIG(RELOCATABLE_RAMSTAGE) +#if !CONFIG(NO_STAGE_CACHE) /* Cache the loaded stage provided according to the parameters. */ void stage_cache_add(int stage_id, const struct prog *stage); /* Load the cached stage at given location returning the stage entry point. */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9deb5bf..e5678ff 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -176,16 +176,13 @@ romstage-$(CONFIG_REG_SCRIPT) += reg_script.c ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
-ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) -ramstage-y += ext_stage_cache.c -romstage-y += ext_stage_cache.c -postcar-y += ext_stage_cache.c -else -ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -postcar-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -endif +ramstage-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c +romstage-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c +postcar-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c
+ramstage-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c +romstage-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c +postcar-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c
romstage-y += boot_device.c ramstage-y += boot_device.c diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index c3d2482..576ae47 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,7 +29,6 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config CBFS_SIZE hex diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index e74f475..b59a7c3 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -39,8 +39,4 @@
postcar-y += ram_calc.c
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c614082..b104b5a 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <program_loading.h> +#include <stage_cache.h> #include <cpu/intel/smm/gen1/smi.h> #include "gm45.h"
@@ -123,6 +124,16 @@ return (void *) top_of_ram; }
+void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE; +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/gm45/stage_cache.c b/src/northbridge/intel/gm45/stage_cache.c deleted file mode 100644 index 47f08c1..0000000 --- a/src/northbridge/intel/gm45/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 3678cb8..dbf91bf 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select POSTCAR_STAGE select POSTCAR_CONSOLE select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index bdf54d2..3a63afc 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -18,6 +18,7 @@
#include <device/pci_ops.h> #include <cbmem.h> +#include <stage_cache.h> #include "haswell.h"
static uintptr_t smm_region_start(void) @@ -34,3 +35,16 @@ { return (void *)smm_region_start(); } + +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index b151e8f..1a4d887 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -30,7 +30,6 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 47014bc..ffeabdc 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -31,8 +31,4 @@
postcar-y += ram_calc.c
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - endif diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 525a5b9..45b9118 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -25,6 +25,8 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stdint.h> +#include <stage_cache.h>
/* Decodes TSEG region size to bytes. */ u32 decode_tseg_size(const u8 esmramc) @@ -88,6 +90,16 @@ return ggc2uma[gms] << 10; }
+void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE; +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c deleted file mode 100644 index 47f08c1..0000000 --- a/src/northbridge/intel/i945/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index b220c2d..93024f6 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -122,9 +122,6 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6)
-/* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 - /* Northbridge BARs */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 485cb27..a058d3f 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -171,11 +171,6 @@ add_fixed_resources(dev, 10); }
-u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - static void mc_set_resources(struct device *dev) { /* And call the normal set_resources */ diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index ba37610..ec036c9 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,6 +23,7 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> +#include <stage_cache.h> #include <cpu/intel/smm/gen1/smi.h> #include "nehalem.h"
@@ -38,11 +39,25 @@ return (u32)smm_region_start(); }
+u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + void *cbmem_top(void) { return (void *) smm_region_start(); }
+void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 37959dd..8acfaf8 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,7 +31,6 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select C_ENVIRONMENT_BOOTBLOCK
config BOOTBLOCK_NORTHBRIDGE_INIT diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 2d16613..8348771 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -30,8 +30,5 @@ romstage-y += early_init.c
postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
endif diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index d1b43aa..33f84a7 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -26,6 +26,8 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/romstage.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stdint.h> +#include <stage_cache.h>
u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -138,6 +140,16 @@
}
+void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE; +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/pineview/stage_cache.c b/src/northbridge/intel/pineview/stage_cache.c deleted file mode 100644 index 47f08c1..0000000 --- a/src/northbridge/intel/pineview/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8..233384c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -444,28 +444,6 @@ MCHBAR32(0x5500) = 0x00100001; }
-static u32 northbridge_get_base_reg(struct device *dev, int reg) -{ - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - -u32 northbridge_get_tseg_base(void) -{ - struct device *dev = pcidev_on_root(0, 0); - - return northbridge_get_base_reg(dev, TSEG); -} - -u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - void northbridge_write_smram(u8 smram) { pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 343ae62..7d5c173 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -20,17 +20,12 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/intel/smm/gen1/smi.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> +#include <stage_cache.h> #include "sandybridge.h"
-#if (CONFIG_SMM_TSEG_SIZE < 0x800000) -# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" -#endif -#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) -# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" -#endif - static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ @@ -43,6 +38,25 @@ return (void *) smm_region_start(); }
+u32 northbridge_get_tseg_base(void) +{ + return ALIGN_DOWN(smm_region_start(), 1*MiB); +} + +u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size() + - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 88b7b56..b488f2c 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -34,10 +34,6 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6)
-/* Intel Enhanced Debug region must be 4MB */ - -#define IED_SIZE CONFIG_IED_REGION_SIZE - /* Northbridge BARs */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index ce43936..a819f57 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -29,7 +29,6 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index cc0a97d..3118b09 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -30,8 +30,5 @@ ramstage-y += northbridge.c
postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
endif diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index be9c10f..fee752d 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -29,6 +29,7 @@ #include <northbridge/intel/x4x/x4x.h> #include <program_loading.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stage_cache.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -134,6 +135,16 @@ return (void *) top_of_ram; }
+void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE; +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c deleted file mode 100644 index 47f08c1..0000000 --- a/src/northbridge/intel/x4x/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5ca0c91..427f757 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -52,7 +52,6 @@ select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if HAVE_ACPI_RESUME select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ea0ad5f..5f1d2f3a 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -73,7 +73,6 @@ select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if HAVE_ACPI_RESUME select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cf3d244..b5073c0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -40,7 +40,6 @@ # Misc options select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 3ad6a8f..d966346 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -13,7 +13,6 @@ romstage-y += memmap.c romstage-y += pmutil.c romstage-y += spi.c -romstage-y += stage_cache.c romstage-y += tsc_freq.c
postcar-y += iosf.c @@ -45,7 +44,6 @@ ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += spi.c -ramstage-y += stage_cache.c ramstage-y += tsc_freq.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 211f476..94e91ca 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -14,6 +14,7 @@ */
#include <cbmem.h> +#include <stage_cache.h> #include <soc/iosf.h> #include <soc/smm.h>
@@ -26,3 +27,16 @@ { return (void *) smm_region_start(); } + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + *base = &smm_base[smm_region_size() - cache_size]; +} diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c deleted file mode 100644 index 4c2a976..0000000 --- a/src/soc/intel/baytrail/stage_cache.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include <soc/smm.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; -} diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7887156..87b9c5b 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -14,7 +14,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bf6b78c..696cf98 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index a79fa46..91a3da0 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -68,9 +68,6 @@ postcar-y += spi.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -postcar-y += stage_cache.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 836fda8..7c53fa6 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -15,11 +15,14 @@
#define __SIMPLE_DEVICE__
-#include <device/pci_ops.h> #include <cbmem.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <soc/smm.h> +#include <stage_cache.h> +#include <stdint.h>
static uintptr_t dpr_region_start(void) { @@ -42,3 +45,15 @@ { return (void *) dpr_region_start(); } + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + u32 offset = smm_region_size(); + offset -= CONFIG_IED_REGION_SIZE; + offset -= CONFIG_SMM_RESERVED_SIZE; + + *base = (void *)(cbmem_top() + offset); + *size = CONFIG_SMM_RESERVED_SIZE; +} diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c deleted file mode 100644 index dc59ab7..0000000 --- a/src/soc/intel/broadwell/stage_cache.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <soc/smm.h> -#include <stage_cache.h> -#include <stdint.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - u32 offset = smm_region_size(); - offset -= CONFIG_IED_REGION_SIZE; - offset -= CONFIG_SMM_RESERVED_SIZE; - - *base = (void *)(cbmem_top() + offset); - *size = CONFIG_SMM_RESERVED_SIZE; -} diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 6dbf35f..4bc6a65 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -59,7 +59,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 99000bb..7931018 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -16,7 +16,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f36d5ca..4f4ec46 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -27,7 +27,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select CPU_INTEL_COMMON
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: [WIP] lib/stage_cache: Rename Kconfig options ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34664/1/src/Kconfig File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/34664/1/src/Kconfig@269 PS1, Line 269: romstage not true since cbmem is initialized in romstage?
Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34664
to look at the new patch set (#2).
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
lib/stage_cache: Refactor Kconfig options
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.
Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache.
There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.
As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option.
Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/stage_cache.h M src/lib/Makefile.inc M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 19 files changed, 30 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/34664/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34664/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34664/2//COMMIT_MSG@12 PS2, Line 12: Platforms with SMM_TSEG=y always need to implement : stage_cache_external_region(). It is allowed to return with a : region of size 0 to effectively disable the cache. It just happens to be that all platforms with SMM_TSEG also implement stage_cache_external_region() but afaict there is no hard requirement to do so.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34664/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34664/2//COMMIT_MSG@12 PS2, Line 12: Platforms with SMM_TSEG=y always need to implement : stage_cache_external_region(). It is allowed to return with a : region of size 0 to effectively disable the cache.
It just happens to be that all platforms with SMM_TSEG also implement stage_cache_external_region() […]
I believe amd/stoneyridge has a hard requirement to have stage_cache for S3 since it uses stage_cache_add_raw() to maintain some platform configuration (volatile storage in S3_DATA_BLOCK). It would be the same with AGESA but it currently uses CBMEM exclusively there, instead of (just slightly more secure) TSEG.
I find the requirement to implement TSEG_STAGE_CACHE support function lesser maintenance burden than adding yet another Kconfig around TSEG to tell explicitly that it is supported.
Besides, without a hard requirement (like with _add_raw() mentioned above), platforms can also 'select NO_STAGE_CACHE'.
BTW: I expect these older intel platforms to evolve to use smm_subregion(SMM_SUBREGION_CACHE,xx) that appears to be the current API for slicing the TSEG. This can obsolete stage_cache_external_region() function entirely.
https://review.coreboot.org/c/coreboot/+/34664/1/src/Kconfig File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/34664/1/src/Kconfig@269 PS1, Line 269: romstage
not true since cbmem is initialized in romstage?
Done
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34664/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34664/2//COMMIT_MSG@12 PS2, Line 12: Platforms with SMM_TSEG=y always need to implement : stage_cache_external_region(). It is allowed to return with a : region of size 0 to effectively disable the cache.
I believe amd/stoneyridge has a hard requirement to have stage_cache for S3 since it uses stage_cach […]
There is followup work that promotes smm_subregion() such that both PARALLEL_MP and TSEG_STAGE_CACHE can build on top of that. Not all work has been pushed for review yet.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig@264 PS3, Line 264: "Cache stages in CBMEM" If this is a user-selectable option and user decides to set it to N and NO_STAGE_CACHE is n, what is the impact?
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig@1164 PS3, Line 1164: HAVE_ACPI_RESUME If you add || !RELOCATABLE_RAMSTAGE here then you won't have to add it to each type of {TSEG,CBMEM}_STAGE_CACHE.
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h File src/include/stage_cache.h:
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h@3... PS3, Line 35: CONFIG(TSEG_STAGE_CACHE) || CONFIG(CBMEM_STAGE_CACHE) Why not !CONFIG(NO_STAGE_CACHE)? Is that because NO_STAGE_CACHE could be N and both these configs can be N too?
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h@5... PS3, Line 54: external Do you intend to update all references of external stage cache to TSEG stage cache as well?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig@264 PS3, Line 264: "Cache stages in CBMEM"
If this is a user-selectable option and user decides to set it to N and NO_STAGE_CACHE is n, what is […]
Disabled cache, there are empty stubs in stage_cache.h. The case of your first comment.
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig@1164 PS3, Line 1164: HAVE_ACPI_RESUME
If you add || !RELOCATABLE_RAMSTAGE here then you won't have to add it to each type of {TSEG,CBMEM}_ […]
True, but the 'depends on' was there already for (new) TSEG_STAGE_CACHE.
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h File src/include/stage_cache.h:
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h@3... PS3, Line 35: CONFIG(TSEG_STAGE_CACHE) || CONFIG(CBMEM_STAGE_CACHE)
Why not !CONFIG(NO_STAGE_CACHE)? Is that because NO_STAGE_CACHE could be N and both these configs ca […]
Exactly, CBMEM_STAGE_CACHE is user settable.
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h@5... PS3, Line 54: external
Do you intend to update all references of external stage cache to TSEG stage cache as well?
Well the API is not restricted to TSEG. Just that at the moment we do not provide other choices. So not here.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig@264 PS3, Line 264: "Cache stages in CBMEM"
Disabled cache, there are empty stubs in stage_cache.h. The case of your first comment.
Done
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig@1164 PS3, Line 1164: HAVE_ACPI_RESUME
True, but the 'depends on' was there already for (new) TSEG_STAGE_CACHE.
Wouldn't it be better to just have the check in a single place especially if we are keeping the scope open for being able to add other ways of having external stage cache?
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h File src/include/stage_cache.h:
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h@3... PS3, Line 35: CONFIG(TSEG_STAGE_CACHE) || CONFIG(CBMEM_STAGE_CACHE)
Exactly, CBMEM_STAGE_CACHE is user settable.
Done
https://review.coreboot.org/c/coreboot/+/34664/3/src/include/stage_cache.h@5... PS3, Line 54: external
Well the API is not restricted to TSEG. Just that at the moment we do not provide other choices. […]
Done
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber, Furquan Shaikh, Damien Zammit, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34664
to look at the new patch set (#5).
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
lib/stage_cache: Refactor Kconfig options
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.
Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache.
There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.
As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option.
Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/stage_cache.h M src/lib/Makefile.inc M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 19 files changed, 29 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/34664/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/34664/3/src/Kconfig@1164 PS3, Line 1164: HAVE_ACPI_RESUME
Wouldn't it be better to just have the check in a single place especially if we are keeping the scop […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
Patch Set 5: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34664 )
Change subject: lib/stage_cache: Refactor Kconfig options ......................................................................
lib/stage_cache: Refactor Kconfig options
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.
Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache.
There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.
As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option.
Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/stage_cache.h M src/lib/Makefile.inc M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 19 files changed, 29 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/Kconfig b/src/Kconfig index 2bb5bfe..6288d0b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -250,12 +250,28 @@ wake. When selecting this option the romstage is responsible for determing a stack location to use for loading the ramstage.
-config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - depends on RELOCATABLE_RAMSTAGE +config TSEG_STAGE_CACHE bool + default y + depends on !NO_STAGE_CACHE && SMM_TSEG help - The relocated ramstage is saved in an area specified by the - by the board and/or chipset. + The option enables stage cache support for platform. Platform + can stash copies of postcar, ramstage and raw runtime data + inside SMM TSEG, to be restored on S3 resume path. + +config CBMEM_STAGE_CACHE + bool "Cache stages in CBMEM" + depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE + help + The option enables stage cache support for platform. Platform + can stash copies of postcar, ramstage and raw runtime data + inside CBMEM. + + While the approach is faster than reloading stages from boot media + it is also a possible attack scenario via which OS can possibly + circumvent SMM locks and SPI write protections. + + If unsure, select 'N'
config UPDATE_IMAGE bool "Update existing coreboot.rom image" @@ -1143,7 +1159,7 @@
config NO_STAGE_CACHE bool - default y if !HAVE_ACPI_RESUME + default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE help Do not save any component in stage cache for resume path. On resume, all components would be read back from CBFS again. diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 089b3fe..a3a58b6 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -21,7 +21,6 @@ select CPU_INTEL_COMMON select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 2af63d6..ced3340 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,7 +19,6 @@ #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 986929c..d8021e6 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -121,7 +121,7 @@ }
/* Adjust available SMM handler memory size. */ - if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) { + if (CONFIG(TSEG_STAGE_CACHE)) { ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE); params->smram_size -= CONFIG_SMM_RESERVED_SIZE; } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 3483c0c..3c7d9fa 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -32,8 +32,7 @@ STAGE_S3_DATA, };
-#if CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) \ - || CONFIG(RELOCATABLE_RAMSTAGE) +#if CONFIG(TSEG_STAGE_CACHE) || CONFIG(CBMEM_STAGE_CACHE) /* Cache the loaded stage provided according to the parameters. */ void stage_cache_add(int stage_id, const struct prog *stage); /* Load the cached stage at given location returning the stage entry point. */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9deb5bf..e5678ff 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -176,16 +176,13 @@ romstage-$(CONFIG_REG_SCRIPT) += reg_script.c ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
-ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) -ramstage-y += ext_stage_cache.c -romstage-y += ext_stage_cache.c -postcar-y += ext_stage_cache.c -else -ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -postcar-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -endif +ramstage-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c +romstage-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c +postcar-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c
+ramstage-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c +romstage-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c +postcar-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c
romstage-y += boot_device.c ramstage-y += boot_device.c diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index c3d2482..576ae47 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,7 +29,6 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config CBFS_SIZE hex diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 3678cb8..dbf91bf 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select POSTCAR_STAGE select POSTCAR_CONSOLE select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index b151e8f..1a4d887 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -30,7 +30,6 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 37959dd..8acfaf8 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,7 +31,6 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select C_ENVIRONMENT_BOOTBLOCK
config BOOTBLOCK_NORTHBRIDGE_INIT diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index ce43936..a819f57 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -29,7 +29,6 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config CBFS_SIZE hex diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 0ba90ef..1c2ec84 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -52,7 +52,6 @@ select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if HAVE_ACPI_RESUME select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ea0ad5f..5f1d2f3a 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -73,7 +73,6 @@ select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if HAVE_ACPI_RESUME select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cf3d244..b5073c0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -40,7 +40,6 @@ # Misc options select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 980d064..76adae1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -14,7 +14,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bf6b78c..696cf98 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 6dbf35f..4bc6a65 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -59,7 +59,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 99000bb..7931018 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -16,7 +16,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f36d5ca..4f4ec46 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -27,7 +27,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select CPU_INTEL_COMMON
-
Arthur Heymans (Code Review) -
Furquan Shaikh (Code Review)
-
Kyösti Mälkki (Code Review)