Change in coreboot[master]: soc/mediatek/mt8195: configure DMA buffer in DRAM

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54052 )

Change subject: soc/mediatek/mt8195: configure DMA buffer in DRAM
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soc/mediatek/mt8195: configure DMA buffer in DRAM

Set DRAM DMA to be non-cacheable to load blob correctly.

Signed-off-by: Rex-BC Chen 
Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54052
Reviewed-by: Hung-Te Lin 
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/mt8195/Makefile.inc
M src/soc/mediatek/mt8195/mmu_operations.c
2 files changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 67ceed3..a04ccf4 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -26,6 +26,7 @@
 romstage-y += ../common/flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/i2c.c i2c.c
+romstage-y += ../common/mmu_operations.c mmu_operations.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += scp.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c
index 7018093..de6e8bc 100644
--- a/src/soc/mediatek/mt8195/mmu_operations.c
+++ b/src/soc/mediatek/mt8195/mmu_operations.c
@@ -29,3 +29,10 @@
    		MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
    dsb();
 }
+
+/* mtk_soc_after_dram is called in romstage */
+void mtk_soc_after_dram(void)
+{
+	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
+			 NONSECURE_UNCACHED_MEM);
+}