[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun, Utkarsh H Patel.
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email )
Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ......................................................................
Patch Set 6:
(4 comments)
File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/78163/comment/a0115179_7e24ba70 : PS6, Line 3: 0xC00
0xC00 is size increase to access higher offsets so IMO no need to wrap under config. […]
Added based on config.
https://review.coreboot.org/c/coreboot/+/78163/comment/22da1f27_ed899ed1 : PS6, Line 54: Offset(0xBA8), /* 0xBA8, MPC - Miscellaneous Port Configuration Register */ : , 30, : HPEX, 1, /* 30, Hot Plug SCI Enable */ : PMEX, 1, /* 31, Power Management SCI Enable */ : Offset(0xBB2), /* 0xBB2, RPPGEN - Root Port Power Gating Enable */ : , 2, : L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ : L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
In Gerrit, the `/*` are not correctly aligned with line 53.
Done
https://review.coreboot.org/c/coreboot/+/78163/comment/de118766_2803f934 : PS6, Line 70: Offset(0xBAC), /* 0xBAC, SMSCS - SMI/SCI Status Register */
Please align `/*`.
Done
https://review.coreboot.org/c/coreboot/+/78163/comment/7e4c5aaa_c365bf25 : PS6, Line 67: #if CONFIG(SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON) : Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */ : #else : Offset(0xBAC), /* 0xBAC, SMSCS - SMI/SCI Status Register */ : #endif
Maybe define a macro for SMSCS?
Done
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Ravishankar Sarawadi (Code Review)