Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: [WIP] soc/intel/tigerlake: Add chipset devicetree ......................................................................
[WIP] soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/chipset.cb 2 files changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44038/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2659357..3baf193 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -89,6 +89,10 @@ Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup.
+config CHIPSET_DEVICETREE + string + default "soc/intel/tigerlake/chipset.cb" + config IFD_CHIPSET string default "tgl" diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb new file mode 100644 index 0000000..4dcd14e --- /dev/null +++ b/src/soc/intel/tigerlake/chipset.cb @@ -0,0 +1,73 @@ +chip soc/intel/tigerlake + register "SaGv" = "SaGv_Enabled" + + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 02.0 alias igpu off end + device pci 04.0 alias dptf off end + device pci 05.0 alias ipu off end + device pci 06.0 alias peg off end + device pci 07.0 alias tbt_pcie_rp0 off end + device pci 07.1 alias tbt_pcie_rp1 off end + device pci 07.2 alias tbt_pcie_rp2 off end + device pci 07.3 alias tbt_pcie_rp3 off end + device pci 08.0 alias gna off end + device pci 09.0 alias npk off end + device pci 0a.0 alias crashlog off end + device pci 0d.0 alias north_xhci off end + device pci 0d.1 alias north_xdci off end + device pci 0d.2 alias tbt_dma0 off end + device pci 0d.3 alias tbt_dma1 off end + device pci 0e.0 alias vmd off end + device pci 10.2 alias cnvi_bt off end + device pci 10.6 alias thc0 off end + device pci 10.7 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.6 alias gspi2 off end + device pci 13.0 alias gspi3 off end + device pci 14.0 alias south_xhci off end + device pci 14.1 alias south_xdci off end + device pci 14.2 alias shared_ram off end + chip drivers/intel/wifi + device pci 14.3 alias cnvi_wifi off end + end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 off end + device pci 16.1 alias heci2 off end + device pci 16.2 alias csme1 off end + device pci 16.3 alias csme2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias sata off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1d.0 alias pcie_rp9 off end + device pci 1d.1 alias pcie_rp10 off end + device pci 1d.2 alias pcie_rp11 off end + device pci 1d.3 alias pcie_rp12 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias pch_espi on end + device pci 1f.1 alias p2sb off end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias thermal off end + end +end
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: [WIP] soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 1:
(1 comment)
I really like this!
https://review.coreboot.org/c/coreboot/+/44038/1/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/44038/1/src/soc/intel/tigerlake/chi... PS1, Line 2: register "SaGv" = "SaGv_Enabled" I don't think this line is supposed to be here
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44038
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/chipset.cb 2 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44038/2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/1/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/44038/1/src/soc/intel/tigerlake/chi... PS1, Line 2: register "SaGv" = "SaGv_Enabled"
I don't think this line is supposed to be here
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 2: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/2/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/44038/2/src/soc/intel/tigerlake/chi... PS2, Line 2: device domain 0 on Maybe add a comment that the SA is the only one left on by default?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/2/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/44038/2/src/soc/intel/tigerlake/chi... PS2, Line 2: device domain 0 on
Maybe add a comment that the SA is the only one left on by default?
Oops, I mean SA, pch_espi and fast_spi
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/2/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/44038/2/src/soc/intel/tigerlake/chi... PS2, Line 2: device domain 0 on
Oops, I mean SA, pch_espi and fast_spi
Done
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... PS3, Line 95: i think you also need: select DRIVERS_INTEL_WIFI
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... PS3, Line 95:
i think you also need: […]
no, I think that DRIVERS_INTEL_WIFI is already set to yes. (see #44936 )
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... PS3, Line 95:
no, I think that DRIVERS_INTEL_WIFI is already set to yes. […]
checked using "make menuconfig":
Symbol: DRIVERS_INTEL_WIFI [=y] │ │ Type : boolean │ │ Prompt: Support Intel PCI-e WiFi adapters │ │ Location: │ │ (1) -> Generic Drivers │ │ Defined at src/drivers/intel/wifi/Kconfig:1 │ │ Depends on: PCI [=y] │ │ Selects: DRIVERS_WIFI_GENERIC [=n]
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... PS3, Line 95:
checked using "make menuconfig": […]
right, but that doesn't show what selected it.
it gets selected by default as a consequence of selecting TIGERLAKE. my suggestion is that since this device tree requires DRIVERS_INTEL_WIFI, we should explicitly select it instead of relying on "default y" for PCIEXP_PLUGIN_SUPPORT.
the dependency graph looks something like this:
src/mainboard/google/volteer/Kconfig: select SOC_INTEL_TIGERLAKE
soc/intel/tigerlake/Kconfig: if SOC_INTEL_TIGERLAKE select ARCH_BOOTBLOCK_X86_32
arch/x86/Kconfig: config ARCH_BOOTBLOCK_X86_32 select ARCH_X86 config ARCH_X86 select PCI
device/Kconfig: if PCI config PCIEXP_PLUGIN_SUPPORT default y
drivers/intel/wifi/Kconfig: config DRIVERS_INTEL_WIFI default y if PCIEXP_PLUGIN_SUPPORT
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... PS3, Line 95:
right, but that doesn't show what selected it. […]
It doesn't need it selected to compile, because all this will do is set up a `struct drivers_intel_wifi_config` with some fields already set, which doesn't require the Kconfig (and thus the .c file to be compiled in), only the header file, which is still accessible. We don't necessarily want to force all Tiger Lake mainboards to have Intel WiFi.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 3:
ping, happy friday!
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 3: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44038/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44038/4//COMMIT_MSG@12 PS4, Line 12: Set a default register value as an example. Where is this set?
https://review.coreboot.org/c/coreboot/+/44038/4/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/44038/4/src/soc/intel/tigerlake/chi... PS4, Line 29: chip drivers/intel/wifi This is what I was referring to in the earlier CL. It isn't a big problem, but I think it might be better to reorganize our CNVi support in coreboot to not require the SoC controller be associated with a chip of its own.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44038/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44038/4//COMMIT_MSG@12 PS4, Line 12: Set a default register value as an example.
Where is this set?
I had this initially as an example (setting SaGv to enabled) but removed it later so this line should probably go.
Tim Wawrzynczak has uploaded a new patch set (#5) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception of some essential devices.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/chipset.cb 2 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44038/5
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 5: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44038/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44038/4//COMMIT_MSG@12 PS4, Line 12: Set a default register value as an example.
I had this initially as an example (setting SaGv to enabled) but removed it later so this line shoul […]
Done
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/44038/3/src/soc/intel/tigerlake/Kco... PS3, Line 95:
It doesn't need it selected to compile, because all this will do is set up a `struct drivers_intel_w […]
Ack
Tim Wawrzynczak has uploaded a new patch set (#9) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception of some essential devices.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie dlaurie@google.com --- A src/soc/intel/tigerlake/chipset.cb 1 file changed, 71 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44038/9
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 9:
Why did `CHIPSET_DEVICETREE` get dropped from Kconfig?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 9:
Patch Set 9:
Why did `CHIPSET_DEVICETREE` get dropped from Kconfig?
Moved to the next patch where it first gets used
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 9:
Patch Set 9:
Patch Set 9:
Why did `CHIPSET_DEVICETREE` get dropped from Kconfig?
Moved to the next patch where it first gets used
This one: https://review.coreboot.org/c/coreboot/+/44039? But, that is a mainboard patch. It shouldn't matter if a mainboard is actually using the aliases e.g. the aliases get used by volteer, but not the intel rvp boards. I think it makes sense to add the Kconfig in this CL.
Tim Wawrzynczak has uploaded a new patch set (#10) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception of some essential devices.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/chipset.cb 2 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44038/10
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 10:
Patch Set 9:
Patch Set 9:
Patch Set 9:
Why did `CHIPSET_DEVICETREE` get dropped from Kconfig?
Moved to the next patch where it first gets used
This one: https://review.coreboot.org/c/coreboot/+/44039? But, that is a mainboard patch. It shouldn't matter if a mainboard is actually using the aliases e.g. the aliases get used by volteer, but not the intel rvp boards. I think it makes sense to add the Kconfig in this CL.
Done.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 10: Code-Review+2
Tim Wawrzynczak has uploaded a new patch set (#11) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/chipset.cb 2 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44038/11
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
Patch Set 11: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44038 )
Change subject: soc/intel/tigerlake: Add chipset devicetree ......................................................................
soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie dlaurie@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44038 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/chipset.cb 2 files changed, 75 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index bf05d37..4df2e85 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -86,6 +86,10 @@ Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup.
+config CHIPSET_DEVICETREE + string + default "soc/intel/tigerlake/chipset.cb" + config IFD_CHIPSET string default "tgl" diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb new file mode 100644 index 0000000..0d2b7a2 --- /dev/null +++ b/src/soc/intel/tigerlake/chipset.cb @@ -0,0 +1,71 @@ +chip soc/intel/tigerlake + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 02.0 alias igpu off end + device pci 04.0 alias dptf off end + device pci 05.0 alias ipu off end + device pci 06.0 alias peg off end + device pci 07.0 alias tbt_pcie_rp0 off end + device pci 07.1 alias tbt_pcie_rp1 off end + device pci 07.2 alias tbt_pcie_rp2 off end + device pci 07.3 alias tbt_pcie_rp3 off end + device pci 08.0 alias gna off end + device pci 09.0 alias npk off end + device pci 0a.0 alias crashlog off end + device pci 0d.0 alias north_xhci off end + device pci 0d.1 alias north_xdci off end + device pci 0d.2 alias tbt_dma0 off end + device pci 0d.3 alias tbt_dma1 off end + device pci 0e.0 alias vmd off end + device pci 10.2 alias cnvi_bt off end + device pci 10.6 alias thc0 off end + device pci 10.7 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.6 alias gspi2 off end + device pci 13.0 alias gspi3 off end + device pci 14.0 alias south_xhci off end + device pci 14.1 alias south_xdci off end + device pci 14.2 alias shared_ram off end + chip drivers/intel/wifi + device pci 14.3 alias cnvi_wifi off end + end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 off end + device pci 16.1 alias heci2 off end + device pci 16.2 alias csme1 off end + device pci 16.3 alias csme2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias sata off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1d.0 alias pcie_rp9 off end + device pci 1d.1 alias pcie_rp10 off end + device pci 1d.2 alias pcie_rp11 off end + device pci 1d.3 alias pcie_rp12 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias pch_espi on end + device pci 1f.1 alias p2sb off end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias thermal off end + end +end
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Caveh Jalali (Code Review) -
Duncan Laurie (Code Review)
-
Furquan Shaikh (Code Review)
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HAOUAS Elyes (Code Review)
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Nick Vaccaro (Code Review)
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Tim Wawrzynczak (Code Review)