New patch to review for coreboot: 7b53ed3 northbridge/intel/fsp_rangeley: Correct MMIO size setting

[Dave Frodin]

Dave Frodin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10047

-gerrit

commit 7b53ed37cb90ae4a160f37d1abc2439212a50f67
Author: Dave Frodin 
Date:   Fri May 1 09:17:43 2015 -0600

northbridge/intel/fsp_rangeley: Correct MMIO size setting

The Rangeley chipset has the MMIO PCI config space feature
    enabled at 0xe0000000-0xefffffff. This is a 256MB space
    which covers all of config space. The ACPI table for
    this space only defines it as being 64MB. This change
    fixes that setting.

Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e
    Signed-off-by: Dave Frodin 
---
 src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
index 6a8c2e0..08dba89 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
+++ b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
@@ -30,7 +30,7 @@ Device (PDRC)
    Name (_UID, 1)

Name (PDRS, ResourceTemplate() {
-		Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x04000000)
+		Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000)
    })

// Current Resource Settings