Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in

[Cliff Huang (Code Review)]

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55127 )

Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
......................................................................

soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in

This change adds S0ix device specific method _DSM ( UUID:
57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in.

Alone with this change, two kernel changes are also required:
https://chromium-review.googlesource.com/2800280
https://chromium-review.googlesource.com/2800281

Once done, substate_requirement_registers is created under
/sys/kernel/debug/pmc_core/
Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to
check the content.

BUG=b:185437326
brya: _DSM method need to implemented in coreboot for PMC requirement
register.

Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398
Signed-off-by: Cliff Huang 
---
M src/soc/intel/common/block/acpi/acpi/globalnvs.asl
M src/soc/intel/common/block/acpi/acpi/pep.asl
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/55127/1

diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index 161381f..d4096d4 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -24,4 +24,5 @@
    UIOR,	8,	// 0x2f - UART debug controller init on S3 resume
    A4GB,	64,	// 0x30 - 0x37 Base of above 4GB MMIO Resource
    A4GS,	64,	// 0x38 - 0x3f Length of above 4GB MMIO Resource
+	LPMR,	32,	// 0x40 - 0x43 Low Power Mode required register Address
 }
diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl
index 2e2a25f..223b899 100644
--- a/src/soc/intel/common/block/acpi/acpi/pep.asl
+++ b/src/soc/intel/common/block/acpi/acpi/pep.asl
@@ -9,6 +9,11 @@
 #define PEPD_DSM_LPI_S0IX_ENTRY 5
 #define PEPD_DSM_LPI_S0IX_EXIT 6

+/* Low Power Mode requirements - data length (byte) */
+#define PEPD_PMC_PWRM_LPM_REQ_DATA_LEN 192
+/* Low Power Mode requirements - data length (bit) */
+#define PEPD_PMC_PWRM_LPM_REQ_BITS_DATA_LEN 1536
+
 External(_SB.MS0X, MethodObj)
 External(_SB.PCI0.LPCB.EC0.S0IX, MethodObj)
 External(_SB.PCI0.EGPM, MethodObj)
@@ -18,6 +23,15 @@
 {
    Name(_HID, "INT33A1")	/* Intel Power Engine */
    Name(_CID, EISAID("PNP0D80"))
+	Name (LBUF, Buffer(PEPD_PMC_PWRM_LPM_REQ_DATA_LEN) {})
+	
+	OperationRegion (LS0I, SystemMemory, LPMR, PEPD_PMC_PWRM_LPM_REQ_DATA_LEN)
+	Field (LS0I, ByteAcc, Lock, Preserve)
+	{
+		/* Low Power Mode Required Register */
+		L0IX, PEPD_PMC_PWRM_LPM_REQ_BITS_DATA_LEN,
+	}
+
    Method(_DSM, 4)
    {
    	/* Low Power Idle S0 helper */
@@ -120,6 +134,18 @@
    		}
    	}

+		If ((Arg0 == ToUUID ("57a6512e-3979-4e9d-9708-ff13b2508972")))
+		{
+			If ((Arg2 == Zero)) {
+				Return (Buffer(One) { 0x03 })
+			}
+			If ((Arg2 == 0x01))
+			{
+				Store (L0IX, LBUF)
+				Return (LBUF)
+			}
+		}
+
    	Return(Buffer(One) {0x00})
    }		// Method(_DSM)
 }			// Device (PEPD)