Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
soc/intel/jasperlake: Enable VT-d and generate DMAR Table
Update UPDs required for the creation of DMAR table.
TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47506/1
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 528ef0f..d420351 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <fsp/util.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> @@ -81,6 +82,17 @@
/* VT-d config */ m_cfg->VtdDisable = 0; + m_cfg->VtdIopEnable = 0x1; + + if (m_cfg->InternalGfx) { + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + } + + if (m_cfg->SaIpuEnable) { + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + }
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE];
Meera Ravindranath has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Removed reviewer Patrick Rudolph.
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Patch Set 1: Code-Review+1
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Patch Set 1: Code-Review+1
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47506/1/src/soc/intel/jasperlake/ro... File src/soc/intel/jasperlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47506/1/src/soc/intel/jasperlake/ro... PS1, Line 85: m_cfg->VtdIopEnable = 0x1; Don't we need to configure VtdBaseAddress[2] when this is enabled? I see references to it in FSP codebase.
Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Ronak Kanabar, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47506
to look at the new patch set (#2).
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
soc/intel/jasperlake: Enable VT-d and generate DMAR Table
Update UPDs required for the creation of DMAR table.
By default coreboot was not generating DMAR table for IOMMU which was resulting in below error message in kernel: DMAR: [Firmware Bug]: No DRHD structure found in DMAR table DMAR: No DMAR devices found These changes will publish DMAR table through ACPI and will not result in the above error.
TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47506/2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47506/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47506/2//COMMIT_MSG@17 PS2, Line 17: BUG=b:170261791 BRANCH=dedede
Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47506
to look at the new patch set (#3).
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
soc/intel/jasperlake: Enable VT-d and generate DMAR Table
Update UPDs required for the creation of DMAR table.
By default coreboot was not generating DMAR table for IOMMU which was resulting in below error message in kernel: DMAR: [Firmware Bug]: No DRHD structure found in DMAR table DMAR: No DMAR devices found These changes will publish DMAR table through ACPI and will not result in the above error.
BUG=b:170261791 BRANCH=dedede TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47506/3
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47506/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47506/2//COMMIT_MSG@17 PS2, Line 17:
BUG=b:170261791 […]
Done
https://review.coreboot.org/c/coreboot/+/47506/1/src/soc/intel/jasperlake/ro... File src/soc/intel/jasperlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47506/1/src/soc/intel/jasperlake/ro... PS1, Line 85: m_cfg->VtdIopEnable = 0x1;
Don't we need to configure VtdBaseAddress[2] when this is enabled? I see references to it in FSP cod […]
Done
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Patch Set 3: Code-Review+1
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Patch Set 3: Code-Review+2
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47506 )
Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ......................................................................
soc/intel/jasperlake: Enable VT-d and generate DMAR Table
Update UPDs required for the creation of DMAR table.
By default coreboot was not generating DMAR table for IOMMU which was resulting in below error message in kernel: DMAR: [Firmware Bug]: No DRHD structure found in DMAR table DMAR: No DMAR devices found These changes will publish DMAR table through ACPI and will not result in the above error.
BUG=b:170261791 BRANCH=dedede TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47506 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com Reviewed-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 13 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 528ef0f..cd70807 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <fsp/util.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> @@ -81,6 +82,18 @@
/* VT-d config */ m_cfg->VtdDisable = 0; + m_cfg->VtdIopEnable = 0x1; + + if (m_cfg->InternalGfx) { + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + } + + if (m_cfg->SaIpuEnable) { + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + } + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE];