[XS] Change in coreboot[main]: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins

[Sean Rhodes (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Martin L Roth, Nick Vaccaro, Nico Huber, Subrata Banik, [e-mail].

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81080?usp=email )

Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
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Patch Set 5:

(3 comments)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/81080/comment/7796d9f7_4b65ea9d :
PS4, Line 837: 	 * which are used for eSPI.
> `... hence we need to switch to GPP_F4 and GPP_F5`. […]

Done

https://review.coreboot.org/c/coreboot/+/81080/comment/b332d9de_3c2e4c76 :
PS4, Line 840: 2
> The comment in `Fsps_Upd. […]

Yeah - looks like a copy/paste from TGL

https://review.coreboot.org/c/coreboot/+/81080/comment/27f81219_1ba9646d :
PS4, Line 838: 
             : 	s_cfg->CnviRfResetPinMux = 0x194ce404;
             : 	s_cfg->CnviClkreqPinMux = 0x294ce605;
> Comments in `Fsps_Upd.h` suggest that both should be 0 for ADL-S which […]

Done (SBL and AMI set them for S too, but guard is good as I doubt anyone would make that combo)