Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
mb/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3
Enbale CNVi in devicetree and add gpio pad configs for CNVi
BUG=none BRANCH=none TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I71146960e0d53dae87946a0365dac6f224a72391 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39464/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4492acb..a43011f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -130,7 +130,7 @@ device pci 0e.0 on end # VMD 0x9A0B
# From PCH EDS(576591) - device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 off end # SensorHUB 0xA0FC diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 30d148a..59ee5ff 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -61,6 +61,10 @@ PAD_CFG_GPO(GPP_C5, 1, PLTRST), PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
+ /* CNVi */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + };
/* Early pad configuration in bootblock */
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
Patch Set 1: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG@9 PS1, Line 9: CNVi this is specific to BT, right? WiFi is enabled here? https://review.coreboot.org/c/coreboot/+/39315
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG@7 PS1, Line 7: mb/tglrvp mb/intel/tglrvp
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG@9 PS1, Line 9: Enbale Enable
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Nick Vaccaro, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39464
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3
Enable CNVi in devicetree and add gpio pad configs for CNVi
BUG=none BRANCH=none TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I71146960e0d53dae87946a0365dac6f224a72391 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39464/2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
Patch Set 2:
(3 comments)
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG@7 PS1, Line 7: mb/tglrvp
mb/intel/tglrvp
Done
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG@9 PS1, Line 9: Enbale
Enable
Done
https://review.coreboot.org/c/coreboot/+/39464/1//COMMIT_MSG@9 PS1, Line 9: CNVi
this is specific to BT, right? […]
This patch turning on CNViBT and configuring GPIOs. 39315's main intention was to add dynamic SSDT for CNViWifi. But both are required for Integrated CNVi functionality to work
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
Patch Set 2: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
Patch Set 2: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3
Enable CNVi in devicetree and add gpio pad configs for CNVi
BUG=none BRANCH=none TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I71146960e0d53dae87946a0365dac6f224a72391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464 Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Caveh Jalali caveh@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 5 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4492acb..a43011f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -130,7 +130,7 @@ device pci 0e.0 on end # VMD 0x9A0B
# From PCH EDS(576591) - device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 off end # SensorHUB 0xA0FC diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index b0c5bc1..fa97a50 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -61,6 +61,10 @@ PAD_CFG_GPO(GPP_C5, 1, DEEP), PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
+ /* CNVi */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + };
/* Early pad configuration in bootblock */
-
Caveh Jalali (Code Review) -
Nick Vaccaro (Code Review)
-
Patrick Georgi (Code Review)
-
Srinidhi N Kaushik (Code Review)