Change in coreboot[master]: mb/google/brask/variants/moli: init overridetree for moli

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: YH Lin, Johnny Li, Zhuohao Lee, Raihow Shi, Felix Held.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 )

Change subject: mb/google/brask/variants/moli: init overridetree for moli
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Patch Set 24: Code-Review+1

(2 comments)

File src/mainboard/google/brya/variants/moli/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/62321/comment/de5fb449_61a2acfc 
PS9, Line 58: 		device ref pcie_rp7 on
            : 			chip drivers/net
            : 				register "wake" = "GPE0_DW0_07"
            : 				register "led_feature" = "0xe0"
            : 				register "customized_led0" = "0x23f"
            : 				register "customized_led2" = "0x028"
            : 				device pci 00.0 on end
            : 			end
            : 		end # RTL8125 Ethernet NIC
> i modify it, but i add register "PcieRpSlotImplemented[7]" = "1" this line in setting of RTL8111, it build fail, so i remove it

Yes, we've been pretty much ignoring that UPD for ADL... the default value is 1 for ADL so it hasn't caused us any trouble, but it we should probably program it correctly.

File src/mainboard/google/brya/variants/moli/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/62321/comment/0803bad2_cb425dec 
PS24, Line 80: 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
FYI, other projects have ended up also adding the `enable_gpio` for the eMMC controller here for RTD3 support to get to a true D3cold state, so I suspect you will want to do the same.