Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 )

Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration
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Patch Set 6:

(1 comment)

File src/soc/intel/common/block/cse/cse.c:

https://review.coreboot.org/c/coreboot/+/61520/comment/fa2e5070_de11b50f 
PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable())
> But only if CSE is in error state & not in a state to accept the GLOBAL RESET command, then global reset should be triggered by setting the registers as described in the guide. Are you referring to something else?

3rd para says.
"Furthermore, if Intel® CSME is in ERROR state, BIOS can use I/O 0xCF9 write of 06h
or 0Eh command with PMC PWRM offset 1048h register bit [20] CF9GR set to perform
the global reset."

For have this capability in platform we need to skip locking the ETR3 bit 31 when CSE is in error state. This check does the same and ensure we enter into else clause and just clear the global reset bit bt leave the locking part.