Change in coreboot[master]: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge
Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36671 )
Change subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge ......................................................................
mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge
On this mainboard variant the PCIe-2-PCI bridge is used a bit different. Adjust the switched off clock lines to match the mainboard configuration.
Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8 Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36671/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index 6a883c6..7ad10f2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -60,12 +60,12 @@ cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd);
- /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream + /* Disable clock outputs 0-3 (CLKOUT) for upstream * XIO2001 PCIe to PCI Bridge. */ struct device *parent = dev->bus->dev; if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) - pci_write_config8(parent, 0xd8, 0x1d); + pci_write_config8(parent, 0xd8, 0x70); }
/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36671 )
Change subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36671/1/src/mainboard/siemens/mc_ap... File src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c:
https://review.coreboot.org/c/coreboot/+/36671/1/src/mainboard/siemens/mc_ap... PS1, Line 68: pci_write_config8(parent, 0xd8, 0x70); if only output 4 is enabled, should the value not be 0x0F?
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36671 )
Change subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36671/1/src/mainboard/siemens/mc_ap... File src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c:
https://review.coreboot.org/c/coreboot/+/36671/1/src/mainboard/siemens/mc_ap... PS1, Line 68: pci_write_config8(parent, 0xd8, 0x70);
if only output 4 is enabled, should the value not be 0x0F?
Yes, you are right. Got the wrong register meaning. Will adjust.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36671
to look at the new patch set (#2).
Change subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge ......................................................................
mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge
On this mainboard variant the PCIe-2-PCI bridge is used a bit different. Adjust the switched off clock lines to match the mainboard configuration.
Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8 Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36671/2
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36671 )
Change subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36671 )
Change subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge ......................................................................
mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge
On this mainboard variant the PCIe-2-PCI bridge is used a bit different. Adjust the switched off clock lines to match the mainboard configuration.
Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8 Signed-off-by: Werner Zeh werner.zeh@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index 6a883c6..f908ab6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -60,12 +60,12 @@ cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd);
- /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream + /* Disable clock outputs 0-3 (CLKOUT) for upstream * XIO2001 PCIe to PCI Bridge. */ struct device *parent = dev->bus->dev; if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) - pci_write_config8(parent, 0xd8, 0x1d); + pci_write_config8(parent, 0xd8, 0x0F); }
/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI
-
Mario Scheithauer (Code Review) -
Patrick Georgi (Code Review)
-
Werner Zeh (Code Review)