Change in coreboot[master]: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19543 )

Change subject: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR
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sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR

Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"

Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/finalize.c
M src/southbridge/intel/bd82x6x/pch.h
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19543/1

diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index c9296fd..1881370 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -65,6 +65,9 @@
    /* GEN_PMCON Lock */
    pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));

+	/* ETR3: CF9GR Lockdown */
+	pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
+
    /* R/WO registers */
    RCBA32(0x21a4) = RCBA32(0x21a4);
    pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 8b22fca..1c4ad45 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -143,6 +143,7 @@
 #define ETR3			0xac
 #define  ETR3_CWORWRE		(1 << 18)
 #define  ETR3_CF9GR		(1 << 20)
+#define  ETR3_CF9LOCK		(1 << 31)

/* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)