Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
Attention is currently required from: Martin Roth. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 )
Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52115/comment/1e3c1a10_acf45f74 PS1, Line 54: HIGH
Not in my experience, no. […]
Reasoning for my comment: Violating timings for PCIe can result in downstream device not being enumerated in some cases which can result in developers debugging issues that wouldn't occur if it was done the right way. It helps with the bringup rather than hurt. This was one of the things that had caused hacks to be added for zork and also had resulted in missed hardware changes until much later. That was the reason I raised this concern to ensure: 1. Either the timings are handled correctly here or 2. The bug you raised captured details about exactly what needs to be done so that it can be picked up by anyone who has cycles.
I will mark this as resolved to let you continue.
https://review.coreboot.org/c/coreboot/+/52115/comment/d0fad776_22441a6e PS1, Line 169: /* EN_PP3300_WLAN */
Yes, I absolutely agree with you. I'll get to that when I'm working on the other bug.
Ack
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Furquan Shaikh (Code Review)