Change in coreboot[master]: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34406 )
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. Patch updates PAD_CFG_GPO* macros to set trig to dasable. It also resolves some problems of creating the PCH/SoC pads configuration, which is based on information from the intelltool dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34406/1
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index e1ddd4b..b3512ba 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -209,25 +209,29 @@ /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
/* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
/* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER)
/* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
/* General purpose input */
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, Paul Menzel, build bot (Jenkins), Nico Huber, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34406
to look at the new patch set (#2).
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. Patch updates PAD_CFG_GPO* macros to set trig to dasable. It also resolves some problems of creating the PCH/SoC pads configuration, which is based on information from the inteltool dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34406/2
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, Paul Menzel, build bot (Jenkins), Nico Huber, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34406
to look at the new patch set (#3).
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. The patch updates PAD_CFG_GPO* macros to set trig to dasable. It also resolves some problems of creating the PCH/SoC pads configuration, which is based on information from the inteltool dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34406/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34406 )
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
Patch Set 3: Code-Review+1
LGTM. +1 to let others take a look.
Hello Patrick Rudolph, Subrata Banik, Angel Pons, Matt DeVillier, Paul Menzel, build bot (Jenkins), Nico Huber, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34406
to look at the new patch set (#4).
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. The patch updates PAD_CFG_GPO* macros to set trig to disable. It also resolves some problems of creating the PCH/SoC pads configuration based on information from the inteltool dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34406/4
Hello Patrick Rudolph, Subrata Banik, Angel Pons, Matt DeVillier, Paul Menzel, build bot (Jenkins), Nico Huber, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34406
to look at the new patch set (#5).
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. The patch updates PAD_CFG_GPO* macros to set trig to disable. It also resolves some problems of creating the PCH/SoC pads configuration based on information from the inteltool dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34406/5
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34406 )
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
Patch Set 5: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34406 )
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
Patch Set 5: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34406 )
Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO* ......................................................................
soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. The patch updates PAD_CFG_GPO* macros to set trig to disable. It also resolves some problems of creating the PCH/SoC pads configuration based on information from the inteltool dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34406 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 0a3e117..7440952 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -227,25 +227,29 @@ /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
/* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
/* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER)
/* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
/* General purpose input */
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Furquan Shaikh (Code Review) -
Martin Roth (Code Review)
-
Maxim Polyakov (Code Review)
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Nico Huber (Code Review)