[S] Change in coreboot[main]: soc/intel/xeon_sp: SoC independent domain and host bridge resource in...

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Shuo Liu, Tim Chu.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79656?usp=email )

Change subject: soc/intel/xeon_sp: SoC independent domain and host bridge resource interface
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Patch Set 2:

(1 comment)

Patchset:

PS2: 
We actually talked a bit about how to get new things upstream in the last
leadership meeting [1]. When new code is written downstream without discussing
it before, risks are generally high that it won't get accepted in the original
downstream state.
> the SoC codes could choose the simplest path to integrate as long as the design is decent

This seems highly subjective. From my point of view the simplest path is
often to re-use as much generic code as possible. And a decent design
wouldn't re-invent any wheel in soc-specific code.

As I mentioned elsewhere, we try to keep coreboot maintained as a whole with
all the support for the different platforms in our tree. This requires tree-wide
refactorings from time to time. For instance CB:78328, the only thing that has
been holding it back for the past half year is the xeon_sp code. Because
somebody re-invented things in xeon_sp code. If there's any sign that this
could happen again with new patches, you risk to have a hard time during
review.

In a way, using the flexibility you mentioned can make coreboot inflexible
as a whole. And that needs to be avoided. We'll have to see if that's a
concern for your new code. Just want to make it understandable why a review
sometimes doesn't turn out well.

[1] Scroll down to ### [PatrickG, Martin] How to present design proposals?
    https://mail.coreboot.org/hyperkitty/list/[e-mail]/message/3YTX...